Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications

Abstract

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.

Modeling and Layout Optimization Techniques for Silicon-Based Symmetrical Spiral Inductors

“…This is a very important prerequisite for device performance comparison at high frequencies as well as circuit optimization. As revealed in Figure 10 of [9], varying the inductor's number of turns is not a suitable solution since the inductance steps between different turns are too large and increase at much higher rates as number of turn increases. For example, from 2 to 3-turn, L increases by 0.8 nH ; from 7 to 8-turn, L increases by 3.54 nH.…”

“…For example, 1.5-turn inductors are designed with widths from 8 to 32 µm and 6.5-turn inductors are designed with widths from 4 to 8 µm. From findings in [9], it would be a waste of expensive testchip resources if 6.5-turn inductors are drawn with width of 32 µm as their substrate losses will be too large, suffering self-resonance at very low frequencies and hence, completely not useful at all. Costly testchip space is better utilized if 1.5-turn symmetrical inductors are designed with widths of 32 µm which will reduce the peak Q-factor frequency and improves the Q-factor of these inductors at low GHz frequencies.…”

“…To fully exploit the cost-effective silicon technologies, area-efficient inductors with optimized performance at the application frequency are required. A reliable and robust methodology that successfully optimized the physical layout of conventional spiral inductors up to 2.5 GHz has been previously proposed and published [9]. However, beyond 2.5 GHz, the inductors experience self-resonance and their inductances increase differently over frequency, making fair performance comparisons of identical inductance extremely difficult and complicated at high frequencies.…”

“…The research outcome in [9] has established new knowledge, revealing that small inductors must be designed with large conductor width to suppress resistive loss achieving improvements in quality factor (Q-factor). As inductance increases, the conductor width has to be reduced to minimize the substrate loss which is more dominant than its resistive loss for these large inductors.…”

“…As inductance increases, the conductor width has to be reduced to minimize the substrate loss which is more dominant than its resistive loss for these large inductors. With these important understandings in mind, this work attempts to develop a scalable symmetrical spiral inductor device model from a streamlined set of test structures designed based on the findings in [9], so that the physical layout of symmetrical spiral inductors can be optimized up to 10 GHz. Without these prior device knowledge, to develop a decent scalable inductor model that encompasses the full design permutations (predicting the effects of inductor's turn, core diameter and width), costly testchip and huge engineering resources would be required.…”