No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

Abstract

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific onresistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

500 V breakdown voltage in β‐Ga2O3 laterally diffused metal‐oxide‐semiconductor field‐effect transistor with 108 MW/cm2 power figure of merit

“…High-voltage ICs' operations can benefit from lateral doublediffused MOSFETs (LDMOSFET) on silicon-on-insulator (SOI) [1][2][3][4]. Also, the architecture of the buried oxide (BOX) must have received significant attention in the SOI high-voltage device to enhance the breakdown voltage (V BR ) since the SOI LDMOSFET suffers from small vertical V BR and is restricted from the active layer and BOX depths [5][6][7][8][9][10][11][12][13].…”

500 V Breakdown Voltage in β-Ga 2 O 3 LDMOSFET With 108 MW/cm 2 Power Figure of Merit

“…High-Voltage ICs operations can bene t from lateral double-diffused MOSFETs (LDMOSFET) on siliconon-insulator (SOI) [1][2][3][4]. Also, the architecture of the buried oxide (BOX) must have been received signi cant attention in the SOI high-voltage device to enhance the breakdown voltage (V BR ) since the SOI LDMOSFET suffers from small vertical V BR and restricted from the active layer and BOX depths [5][6][7][8][9].…”