A 0.18&amp;#x03BC;m SOI BCD technology for automotive application

Yang, Hao; Sim, Poh Ching; Toner, B.; Frank, M.; Ackermann, M.; Tan, Andy; Kuniss, Uta; Kho, Elizabeth Ching Tee.; Doblaski, J.; Hee, E. G.; Liew, Madelyn; Hoelke, A.; Wada, S.; Oshima, Takashi

doi:10.1109/ispsd.2015.7123418

Cited by 13 publications

(5 citation statements)

References 5 publications

(4 reference statements)

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“…This is because the doping concentration of 2x SJ is allowed to be increased according to the SJ theory. In the same figure, we are also plotting device performances as reported previously by XFAB[14] as well as NXP[21], STM[17], Renesas[22], UESTC/CSMC[23] and On Semi[24]. For the double SJ drift device type, the demonstrated performance outperforms these devices.…”

mentioning

confidence: 57%

“…The positive voltage on the substrate needs to be carefully isolated from a grounded heat sink. X-FAB is currently offering an 180nm SOI technology with a PSOI option up to 200V [13], [14], [15] and has recently released the 400V rated devices. This technology is based on a p-substrate with the substrate sitting at a ground potential and therefore attaching a heat sink, or heat convection materials (such as Copper) is straightforward.…”

Section: A History and Commercial Implementationsmentioning

confidence: 99%

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High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

Antoniou

Udrea

Tee³

et al. 2022

IEEE Trans. Electron Devices

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Partial SOI (PSOI) is a widely recognized technology suitable for High Voltage (HV) architectures for Power Integrated Circuits (PICs). Despite the added process complexity compared to SOI RESURF, this technology offers a wider range of voltage ratings due to the action of the depletion layer in the Handle Wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-dimensional designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low on-state resistance and reduced selfheating are essential requirements. This work presents a PSOI technology platform with voltage ratings ranging from 45 to 400V while providing low on-state resistance, good hot carrier injection stability as well as Electrostatic Discharge (ESD) capability of the HV devices. For example, for a 375V rated LDMOSFET, this technology achieves an on-state resistance of 1435mΩ.mm 2 , an over 50% improvement compared to the state-of-the-art SOI technologies while maintaining competitive reliability.

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mentioning

confidence: 57%

Section: A History and Commercial Implementationsmentioning

confidence: 99%

High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

Antoniou

Udrea

Tee³

et al. 2022

IEEE Trans. Electron Devices

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“…For ASIC implementation the XFAB 180 nm XT018 technology has been selected. It's a Silicon-on-Insulator (SOI) process with technology libraries that are qualified specifically designed for a wide temperature range from −40 • C up to 175 • C [4]. Moreover, the relatively large node size of 180 nm and the use of a SOI technology results in a low leakage, which reduces the power consumption and resulting self-heating [11].…”

Section: Asic Layoutmentioning

confidence: 99%

Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology

Stuckenberg

Rucker

Rother

et al. 2021

2021 IEEE Nordic Circuits and Systems Conference (NorCAS)

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Broadband powerline communication systems using Orthogonal Frequency Division Multiplexing (OFDM) can utilize existing power lines to transmit data packets alongside power distribution. Recent standards focus towards high speed multi-media in-house streaming. With improvements towards robustness and throughput new standards increase the speed and reliability of in-house powerline systems. A very different approach is the use of powerline communication systems in a deep drilling environment where temperatures of more than 150 • C and pressure levels up to 30 000 psi are present. Typical applications in this environment usually do not require more than several kbit/s per node and are more reliant on a stable and continuous connection. Here, a powerline communication system can reduce the amount of wiring needed and increase communication robustness significantly. This work provides a harsh environment suitable, reliable and standard compliant communication ASIC that is manufactured in XFAB 180 nm Silicon-On-Insulator (SOI) technology allowing operating temperatures of up to 175 • C. The die size is 5.25 mm x 5.25 mm and contains a complete Homeplug 1.0 communication stack with an environment for boot, interfacing and debugging. The data rate is as high as 6.1 Mbit/s using the fastest transmission mode and reaches the theoretical maximum of 0.55 Mbit/s in the robust OFDM (ROBO) mode which is of particular interest for harsh environment applications. To the best of the authors knowledge, this is the first OFDM-based powerline communication ASIC which is particularly designed for harsh environment.

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“…An improved overall architecture is presented to further enhance the performance, culminating in more than tenfold improvement of the BJT trigger current at grounded gate conditions. This improved Hybrid Source LDMOS device architecture has been implemented on an existing 0.18µm BCD on SOI Automotive Process [5]. In addition to demonstrating performance improvement, supplementary insight into the creation of the Hybrid Source and its underlying mechanisms is provided.…”

Section: Introductionmentioning

confidence: 99%

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

Toner¹,

Eisenbrandt

Frank

et al. 2021

IEEE J. Electron Devices Soc.

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A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific onresistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

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A 0.18μm SOI BCD technology for automotive application

Cited by 13 publications

References 5 publications

High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

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