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The COM2 SiGe modular BiCMOS technology has been developed to allow efficient design and manufacturing of digital, mixed-signal, and RF integrated circuits, as well as enabling system-on-chip (SOC) integration. The technology is based on the 0.16pm COM2 digital CMOS process which features 1.5V NMOS and PMOS transistors with 2.4nm gate oxide, 0.135pm gate length, and up to 7 metal levels. Technology enhancement modules including dense SRAM, SiGe NPN bipolar transistor, and a variety of passive components have been developed to allow the COM2 technology to be cost-effectively optimized for a wide range of applications.

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In this paper a merged 2.5 V and 3.3 V high performance 0.25 pm CMOS ASIC technology is presented. This technology features a 50 8, gate oxide, n+-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45X in circuit performance and 3.7X in packing density is achieved over our previous generation 0.35 pm CMOS technology by device scaling and aggressive design rules. The nominal ring oscillator delay time is 38 ps. INTRODUCTIONThis paper describes a merged 2.5 V and 3.3 V 0.25 pm CMOS technology where transistors with both voltage grades are integrated on the same chip with the addition of only one extra implant mask level. This approach allows the implementation of 2.5 V and 3.3 V functional blocks on the same chip. Furthermore, process technologies for each supply voltage grade need not be developed, transferred, or qualified for manufacturing separately. All transistors utilize a 50 8, S i 0 2 gate dielectric. Aggressive interconnect and isolation design rules are employed ,to achieve a factor of 3.7 and 5.7 improvement in packing density over our previous generation 0.35 p m [ l ] and 0.5 pm [2] CMOS technologies, respectively. Nominal gate delays of 38 ps for an unloaded ring oscillator is measured. These improvements in performance and packing density have been obtained through the use of (i) a scaled LOCOS isolation ( Fig. 1) scheme that allows the active area to tub edge separation to be reduced below 0.40 pm (Fig. 2), (ii) high energy implants to define the n and p tubs, (iii) a 50 8, gate oxide used for all transistors, (iv) hard-mask gate processing and deep-UV photolithography with Le# control of 3 0 = 0.04 pm, (v) 415 level metal routing with metal design rules optimized for ASIC applications (Fig. 3). THE PROCESSThe starting wafers consist of 5.0 pm p-epi grown on a (100) pf Si substrate. The isolation scheme used is a low cost scaled LOCOS process. Active areas are defined by patterning the LOCOS stack. Pad-Si02 and Si3N4 thickness as well as the field-oxide (FOX) growth conditions are optimized to achieve a birds beak length of 600 8, as shown in the SEM micrograph Fig. 1. The grown field-oxide thickness is 2500 A. We note that the encroachment of the field-oxide into the active areas (i.e., birds beak length) is mostly determined by the pad-Si02 thickness and the field-oxide growth conditions rather than the Si3 N4 thickness. No LOCOS stack lifting is observed after the field-oxide is grown. After nitride removal a sacrificiallscreen Si02 layer is grown. N-and P-tubs are formed by high energy implants. The use of high energy implant methodology reduces the total number of process steps as compared with conventional twin-tub flow [3]. The N-tub is defined by a deep phosphorus implant which determines the tub depth. Another shallower phosphorus implant serves as a channel-stop for the PMOS devices. Arsenic and BF, are implanted to set the threshold voltage of the PMOS transistor. The P-tub is created by a deep boron implant. A second boron implant is performed for punch-through suppressio...