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The ISFET sensing membrane is in direct contact with the electrolyte solution, determining the starting sensitivity of these devices. A SiO2 gate dielectric shows a low response sensitivity and poor stability. This paper proposes a comprehensive identification of different high-k materials which can be used for this purpose, rather than SiO2. The Gouy-Chapman and Gouy-Chapman-Stern models were combined with the Site-binding model, based on surface potential sensitivity, to achieve the work objectives. Five materials, namely Al2O3, Ta2O5, Hfo2, Zro2 and SN2O3, which are commonly considered for micro-electronic applications, were compared. This study has identified that Ta2O5 have a high surface potential response at around 59mV/pH, and also exhibits high stability in different electrolyte concentrations. The models used have been validated with real experimental data, which achieved excellent agreement. The insights gained from this study may be of assistance to determine the suitability of different materials before progressing to expensive real ISFET fabrication. Keywords:High-k material ISFET ISFET/electrolyte models pH sensitivity Surface stability

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The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

This paper presents a study of optimizing input process parameters on leakage current (IOFF) in silicon-on-insulator (SOI) Vertical Double-Gate [1] Metal Oxide Field-Effect-Transistor (MOSFET) by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF) value. An orthogonal array [2], main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF). Based on the results, the minimum leakage current ((IOFF) of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION) value at 434 µA/µm. Both the drive current (ION) and leakage current (IOFF) values yield a higher ION/IOFF ratio (48.22 x 10 6 ) for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.