The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

Perovskite solar cell (PSC) technologies have recently become a popular research topic. The hole transport layers (HTL) are important in establishing stable and efficient PSC by regulating charge absorption, interlayer recombination losses, and band alignment. Spiro-OMeTAD was extensively used as the HTL to fabricate highly efficient PSCs. Despite Spiro-OMeTAD having the benefit of providing high PCEs, it is costly, hazardous to the ecology, and cannot provide high efficiencies in the lack of additional additives that can reduce their stabilities. Inorganic HTL, specifically nickel oxide (NiO), has garnered much interest due to its low-cost, enhanced mobility, and strong stability to attain high efficiency. This study investigated different precursor solutions of NiO synthesis (Method I, II, and III) and deposited using the spin coating approach. The films were annealed at different annealing temperatures (400°C, 550°C, and 700°C) and evaluated by X-ray powder diffraction (XRD), UV-Vis spectroscopy, and Scanning electron microscopy (SEM) to test their structural, morphological, and optical characteristics, respectively. The findings of XRD revealed that a higher annealing temperature increases the crystallite size and decreases the microstrain through the study from Scherrer’s and Williamson-Hall’s (WH) equations. From the SEM analysis, the films show uniformity, large crystals, and agglomeration of particles. The annealing temperature from 400°C to 700°C reduced bandgap energy from 3.6 eV to 2.1 eV. According to the result, NiO produced at an annealing temperature of 700°C (Method I) exhibited the best characteristics and might be a viable option for HTL in PSCs.

The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.

An improvement on redundancy to achieve high compression ratio in video coding is developed. Block Matching Motion Estimation (BMME) techniques have been particularly used in various coding standards. In the BMME, search patterns with different shapes or sizes and the center-biased characteristics of motion vector (MV) have large impact on the search speed (search points) and peak signal-to-noise ratio (PSNR) as the quality of video images. These basic algorithms are Full Search and other two fast search methods. The Cross Diamond Search (CDS) algorithm was designed to fit the cross-center-biased (CCB) MV distribution characteristics of the real-world video sequences. CDS compares favorably with the other algorithms for low motion sequences in terms of speed, quality and computational complexity.

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Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with opened and shorted guard ring structure.

SUMMARYnMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18 µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84 µm, the detection area of 10 × 10 µm 2 , the PAD size for RF probing of 30 × 30 µm 2 , and with the guard ring structure. The maximum bandwidth of 8.4 GHz was achieved along with the gain-bandwidth product of 280 GHz.

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