Analysis of analog and RF behaviors in junctionless double gate vertical MOSFET

Abstract

The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

“…In this structure, there is no abrupt change of doping distribution between the source/drain and the channel, so it is easy to process and reduce the degradation of the subthreshold swing, threshold voltage shift, and drain induction barrier lowering (DIBL) caused by the transistor size reduction [8][9][10][11]. Recently, a junctionless structure has been developed in various forms to reduce such a short channel effect [12][13][14]. However, due to the scaling effect, the reduction of transistor size inevitably decreases the gate oxide thickness, which caused the short channel effect by the hot carrier, such as the increase of parasitic current to the gate oxide and the increase of power consumption [15][16].…”

Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

“…The existing three-dimensional structure mainly used an inversion-type MOSFET using a junction-based structure with different doping type and concentration between source/drain and channel, but recently reached the limit of the technology of forming a junction with decreasing channel length to nano unit [5][6][7][8]. The transistor developed to solve this problem is a junctionless MOSFET [9,10]. This structure is an accumulation-type MOSFET that overcomes process limitations by doping the source/drain and channel in the same type and concentration [11][12][13].…”

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

“…In particular, the double gate structure is developing the junctionless accumulation type, doping the source, drain and the channel equally as well as the junction-based inversion type [6]- [10]. It is reported that the process is easier and the short channel effects are reduced further in the junctionless accumulation type than the inversion type DGMOSFET [11]- [13]. Scaling not only increases channel doping but also greatly reduces the gate oxide thickness.…”