Performance analysis of ultrathin junctionless double gate vertical MOSFETs

Abstract

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

Analogue properties of junction-less strained dg-mosfet

“…Ionization effects such as the kink effect and parasitic bipolar action may have an enormous impact on the gd value in most transistors [13]. To overcome this issue, the device employs a very thin body (~10nm), so that the strained channel could be fully depleted at certain input V gs [14]. With the top and bottom gate configuration, engulfing the fully depleted strained channel, those aforementioned impact ionization effects could be further minimized.…”

“…The device with WF = 4.8 eV has the lowest g d , estimated at 0.04 mS/µm. In regard of CMOS design consideration, the transistors with low g d is always preferable for attaining high gain [15].…”

Work function variations on electrostatic and RF performances of JLSDGM Device

“…Next, the strained SiGe and Si layers were heavily doped with 1x10 17 cm -3 of Arsenic dose (n-type). Tungsten silicide (WSi 2 ) layer was opted for the gate material due to its superior tunable WF [31]- [33]. The top and bottom gate configuration was intended to boost the gate controllability over the strained channel, thereby improving the carrier's mobility.…”

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

“…In this structure, there is no abrupt change of doping distribution between the source/drain and the channel, so it is easy to process and reduce the degradation of the subthreshold swing, threshold voltage shift, and drain induction barrier lowering (DIBL) caused by the transistor size reduction [8][9][10][11]. Recently, a junctionless structure has been developed in various forms to reduce such a short channel effect [12][13][14]. However, due to the scaling effect, the reduction of transistor size inevitably decreases the gate oxide thickness, which caused the short channel effect by the hot carrier, such as the increase of parasitic current to the gate oxide and the increase of power consumption [15][16].…”