We describe the realization of a fully-electronic label-free temperature-controlled biosensing platform aimed to overcome the Debye screening limit over a wide range of electrolyte salt concentrations. It is based on an improved version of a 90 nm CMOS integrated circuit featuring a nanocapacitor array, readout and A/D conversion circuitry, and an FPGA-based interface board with NIOS II soft processor. We describe the chip's processing, the mounting, the microfluidics, the temperature control system, as well as the calibration and compensation procedures to reduce systematic errors, which altogether make up a complete quantitative sensor platform. Capacitance spectra recorded up to 50-70 MHz are shown and successfully compared to predictions by FEM numerical simulations in the Poisson-Drift-Diffusion formalism. They demonstrate the ability of the chip to reach high upper frequency of operation, thus overcoming the low-frequency Debye screening limit at nearly physiological salt concentrations in the electrolyte, and allowing for detection of events occurring beyond the extent of the electrical double layer. Furthermore, calibrated multi-frequency measurements enable quantitative recording of capacitance spectra, whose features can reveal new properties of the analytes. The scalability of the electrode dimensions, inter-electrode pitch and size of the array make this sensing approach of quite general applicability, even in a non-bio context (e.g. gas sensing).
We propose a new approach to describe in commercial TCAD the chemical reactions that occur at dielectric/electrolyte interface and make the ion sensitive FET (ISFET) sensitive to pH. The accuracy of the proposed method is successfully verified against the available experimental data.\ud
We demonstrate the usefulness of the method by performing, for the first time in a commercial TCAD environment, a full 2-D analysis of ISFET operation, and a comparison between threshold voltage and drain current differential sensitivities in the linear and saturation regimes. The method paves the way to accurate\ud
and efficient ISFET modeling with standard TCAD tools
This paper presents a fully-adaptive high-speed serial interface designed in 28 nm planar CMOS technology for future MIPI-compliant automotive microcontrollers operating at 12 Gb/s over long-reach channels. The transmitter has a voltage-mode driver and operates at full rate featuring an 8-tap feed-forward equalizer with tap programmability of 1/16. Transmitter's output impedance tuning is performed through activation of different driver replicas. The half-rate receiver features an analog front-end which comprises a variable-gain amplifier and a continuous-time linear equalizer. The subsequent decision-feedback equalizer has 3 programmable taps, the first of which is loop-unrolled to relax timing constraints. Another amplifier is embedded in the DFE's summing node. We employ transistor-level simulations to assess the capability of the interface to optimally adapt to realistic channels: The DFE taps and the data sampling phase are automatically adapted by means of a behavioural implementation of an LMS algorithm based on information gathered through error sampling. Such an interface was simulated on channels representing likely MIPI A-PHY to-be-defined specifications featuring up to 33 dB loss at 6 GHz.
Significant advances have been made in solid-state imaging technologies that expand the visual experience and capability to levels far beyond the limitation of human eyes. Various applications range from life enhancement such as smartphone, AR/VR, surveillance, and automobile, to visions in hard-to-reach places like biomedical imaging. While the CMOS image-sensor (CIS) market remains fastest growing, new technologies and new materials are opening up new dimensions, leading to new applications and new challenges.
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