Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes

Dazzi, Martino; Palestri, Pierpaolo; Rossi, Davide; Bandiziol, Andrea; Loi, Igor; Bellasi, David E.; Benini, Luca

doi:10.1109/iscas.2018.8351893

Cited by 8 publications

(10 citation statements)

References 17 publications

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“…Fig. 3 depicts the detailed architecture of the 40:1 serializer [22]. According to the counter output synchronizing to "Clk fll/4", the multiplexer selects a set of 8-bits over the 40bit word.…”

Section: Serdes Interfacementioning

confidence: 99%

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A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

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The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated endnode systems. This trend also reveals growing demands for highspeed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This paper presents a low-swing transceiver for the energy-efficient and low power chip-to-chip communication fully integrated within an IoT end-node Systemon-Chip, fabricated in CMOS 65nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves 8.46x higher energy efficiency at 15.9x higher performance than a traditional microcontroller interface such as a single-SPI.

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Section: Serdes Interfacementioning

confidence: 99%

“…The driver is composed of a voltage-mode differential driver with a chain of inverters acting as a pre-driver [22] (Fig. 4).…”

Section: Serdes Interfacementioning

confidence: 99%

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

Self Cite

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“…The microstrip features are computed from the line's geometry and material parameters following the approach defined in [31][32][33][34][35][36] for single-ended lossy microstrips, or extended to the coupled case according to [37,38], and then used to extract its per-unit-length parameters r( f ), l( f ), c( f ), g( f ) considering dielectric losses and skin effect, all of which are among the main contributors to ISI [4].…”

Section: Communication Channelmentioning

confidence: 99%

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

Menin¹,

Bernardi²,

Cortiula³

et al. 2020

Adv. sci. technol. eng. syst. j.

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We describe an efficient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model's complexity.

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“…Approximate computing is a promising approach for energy savings, especially, in conjunction with other state-of-the-art energy efficient techniques [10] - [14]. It exploits the inherent error resilience of healthcare applications and relaxes the equivalence margin between specification and implementation [16].…”

Section: Approximate Digital Compressed Sensingmentioning

confidence: 99%

“…These limited energy resources tend to reduce their processing capability. Recently, many ultra-low power processors [10] [11], hybrid [12] or non-volatile memories [13] and system-onchips (SoCs) with integrated radio transceivers [14] have been developed. However, they contribute to quite meager energy efficiency gains on edge devices for big data analytics.…”

Section: Introductionmentioning

confidence: 99%

ApproxCS: Near-Sensor Approximate Compressed Sensing for IoT-Healthcare Systems

Siddique¹,

Hasan²,

Khalid³

et al. 2018

Preprint

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Internet of Things (IoTs) is an emerging trend that has enabled an upgrade in the design of wearable healthcare monitoring systems through the (integrated) edge, fog, and cloud computing paradigm. Energy efficiency is one of the most important design metrics in such IoT-healthcare systems especially, for the edge and fog nodes. Due to the sensing noise and inherent redundancy in the input data, even the most safety-critical biomedical applications can sometimes afford a slight degradation in the output quality. Hence, such inherent error tolerance in the bio-signals can be exploited to achieve high energy savings through the emerging trends like, the Approximate Computing which is applicable at both software and hardware levels. In this paper, we propose to leverage the approximate computing in digital Compressed Sensing (CS), through low-power approximate adders (LPAA) in an accurate Bernoulli sensing based CS acquisition (BCS). We demonstrate that approximations can indeed be safely employed in IoT-healthcare without affecting the detection of critical events in the biomedical signals. Towards this, we explored the trade-off between energy efficiency and output quality using the state-of-the-art lp 2d RLS reconstruction algorithm. The proposed framework is validated with the MIT-BIH Arrhythmia database. Our results demonstrated approximately 59% energy savings as compared to the accurate design.

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Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes

Cited by 8 publications

References 17 publications

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

ApproxCS: Near-Sensor Approximate Compressed Sensing for IoT-Healthcare Systems

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