The demand for low-power equalisation at high data rates in serial-link receivers has prioritised the issue of power consumption. This high demand has also involved the phase-locked loop (PLL) and clock and data recovery (CDR) circuits. This propelled efforts to further optimise the PLLs and CDRs building blocks and to pursue low-power solutions. A charge-based phase interpolator (PI) is presented. It employs charge-steering circuits in order to reduce the power typically consumed by its current-based counterpart. Implemented in 65-nm CMOS technology, a 6-bit charge-based PI consumes 180 μW at 1-V supply and 5-GHz clock.
Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for lowpower applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e. phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a lowdropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350µW at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4×-15× lower than state-of-the-art (SoA) digital-totime converters (DTCs) and an integral non-linearity (INL) of 2.5×-3.1× better than SoA PIs, striking a good balance between linearity and energy efficiency.
The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated endnode systems. This trend also reveals growing demands for highspeed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This paper presents a low-swing transceiver for the energy-efficient and low power chip-to-chip communication fully integrated within an IoT end-node Systemon-Chip, fabricated in CMOS 65nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves 8.46x higher energy efficiency at 15.9x higher performance than a traditional microcontroller interface such as a single-SPI.
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