A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

“…The design and analysis of HSIOs comprising a variety of complex equalization techniques require efficient system-level models capable of producing fast and accurate predictions of the system behaviour. Extending the work presented in [1] and relating it with contributions from [19,27], this paper shows how fast system-level simulations of high-speed serial interfaces can be performed with a simple modular model. The paper proceeds as follows: Section 2, starting from the architecture of a generic HSSI, describes the numerical model, how it evaluates performance accounting for jitter and how fully-adaptive equalization is computed; Section 3 shows some sample simulation results and comparisons with post-layout transistor-level simulations, demonstrating the capabilities of the proposed approach; finally, conclusions are drawn in Section 4.…”

“…In order to accurately model the system performance of a generic HSIO device, the general model depicted in Figure 1 and extensively described in [19] is considered: Denoting by the subscript i the sampling instant t b = iT b (where T b corresponds to a bit period, i.e. one Unit Interval UI), the data sequence d i is sent by the differential transmitter tx at a bitrate f b = 1/T b , optionally implementing FFE; the channel, whose sampled pulse response is h ch,i , can be modelled either as two independent single-ended lines or as a coupled differential line; the receiver rx contains an amplifier, a CTLE and a DFE, and produces the analog voltage y i ; the slicer makes decisions on such a voltage (…”

“…Therefore, calibration and adaptation strategies are required in order to find the optimal equalization parameters for the actual channel [13,[15][16][17]. Full adaptation automatically performs such a task, and is usually implemented in the form of Sign-Sign Least-Mean Squares (SS-LMS) algorithms due to the short time required to adjust the equalization parameters and the simplicity of their realization [11,12,15,16,[18][19][20][21].…”

“…Such a complexity cannot be conveniently handled through transistor-level descriptions because of the extremely long simulation times that they require. Therefore, various system-level models have been proposed in the last decades to aid the design of HSSIs, mainly using statistical techniques [19,[23][24][25][26]. Such tools are very important for the initial system-level assessment in the design of chip-to-chip HSIOs for selecting design specifications such as the number of equalization taps, the amount of high-frequency content that needs to be equalized, evaluating the Signal-to-Noise Ratio (SNR) and the overall jitter that can be tolerated without degrading the BER.…”

“…Figure 1: Scheme of a generic high-speed serial interface with equalization: h tot,i is the overall pulse response of the TX (FFE+driver) + channel + RX (ampli-fier+CTLE+DFE) system; c is a generic equalization parameter (e.g. a filter tap), which may be either statically set or automatically adapted [19].…”