During the design of 2.5D and 3D integrated systems the thermal management of the whole system is important, especially in high performance systems with combinations of processor and memory dies utilizing the Wide I/O memory interface. Because cooling solutions could be very expensive they should be considered in very early design cycles. For example, the decision if the system is implemented as a real stacked system or using an interposer strongly influences the required cooling solution. Furthermore, high performance systems with data transfer rates in the range of 100 Gbit/s to 400 Gbit/s between processo r and memory req uire an early and fast floorplan calculation to determine and optimize the heat distribution within the system (i.e., dies and package).In this paper, an appropriate floorplanner with direct access to an octree based finite element solver for the calculation of the heat distribution of the whole system is presented. Our approach allows an efficient design space exploration. The thermal simulation on system level, including heatsink and package, makes it unnecessary to manually set the boundary conditions of the chips. Thus, this approach prevents possible errors caused by this step.To illustrate the new analysis and optimization approach, it is applied to a Wide I/O 2.5D or 3D integrated system, respectively.
3D system integration is a fast growing field that encompasses different types of technologies. [1] The technology chosen for a specific application will be selected according to the required electrical performance of the systems, the footprint, cost and time to market. Other important factors are the boundary conditions given for the specific components e.g. die size, integration compatibility, component availability (wafer vs. bare die) and testability. The paper discusses a specific 3D image sensor system for automotive applications. The system is based on wafer level technology using silicon interposer with Through Silicon Vias (TSV´s), a flip chip assembled sensor element and a microcontroller. The specific system concept, the technical solution and results are discussed
In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window
3D system integration is a fast growing field that encompasses different types of technologies. The technology chosen for a specific application will be selected according to the required electrical performance of the systems, the footprint, cost and time to market. Other important factors are the boundary conditions given for the specific components e.g. die size, integration compatibility, component availability (wafer vs. bare die) and testability. The paper discusses a specific 3D image sensor system for automotive applications. The system is based on wafer level technology using silicon interposer with through silicon vias (TSV's), a flip chip assembled sensor element and a microcontroller. The specific system concept, the technical solution and results are discussed
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.