This work describes the design of a transmitter for a\ud
10 Gbps serial interface to be used in automotive Electronic Control\ud
Units. The data rate is chosen in order to assess the design\ud
challenges in automotive environment at this frequency. The focus\ud
will be mainly on challenges related to transistor level design\ud
using a standard 28 nm technology, nevertheless a system level\ud
overview will be also given. The proposed transmitter features\ud
feed-forward equalization with 8 taps (1 pre-cursor and 6 postcursors,\ud
plus the main tap), whose strength is programmable with\ud
16 discretization steps, optimizing the transmitter adaptability\ud
with reduced area. The proposed architecture is also able to\ud
tune its output impedance independently from the choice of the\ud
weights of the equalization tap. It features a 300 mV peak-topeak\ud
eye diagram with 16 equalization levels and achieves a\ud
remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit\ud
for the predriver+driver)
This paper presents a First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter (LO TDC). The architecture and governing equations of the LO TDC are described. In order to show the effect of noise shaping on the resolution of the TDC, the system "LO TDC plus moving average filter" is introduced. An equation to predict the resolution of the system "LO TDC plus filter" is given. Then, the Matlab model of the system "LO TDC plus filter" is illustrated briefly, and some example of simulated input-output characteristics are shown. Afterwards, the implementation of the LO TDC on an FPGA is described. A comparison between the predicted, simulated and measured values of the resolution of the system "LO TDC plus filter" is reported. Finally, we show spectra of the output signals of the LO TDC from experiments and simulations.
We describe an efficient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model's complexity.
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