Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm

Bandiziol, Andrea; Grollitsch, Werner; Brandonisio, Francesco; Bassi, Matteo; Nonis, Roberto; Palestri, Pierpaolo

doi:10.1109/iscas.2018.8351310

Cited by 7 publications

(6 citation statements)

References 18 publications

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“…A typical DFE has summers depending on the number of interleaves (shown as a gray line in Fig. 2) [4,18,19,20,23,24,25]. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer.…”

Section: Proposed Dfe Architecturementioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unitinterval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm 2 . Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.

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Section: Proposed Dfe Architecturementioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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“…In this paper we focus on the adaptive equalization of the channel. Details on the CDR algorithm are reported in [12].…”

Section: Transceiver Architecturementioning

confidence: 99%

“…The receiver [12] operates at half rate with a 1-tap speculative decision-feedback equalizer (DFE) featuring other 2 non-speculative taps, all programmable with steps of 7 mV. A programmable variable gain amplifier (VGA) at the input adapts the voltage swing for the subsequent continuous-time linear equalizer (CTLE).…”

Section: Transceiver Architecturementioning

confidence: 99%

“…A programmable variable gain amplifier (VGA) at the input adapts the voltage swing for the subsequent continuous-time linear equalizer (CTLE). In addition to the architecture presented in [12], Fig. 1 shows two error samplers with variable threshold dLev (other two are in the odd path) used to perform full adaptation as described in the following section.…”

Section: Transceiver Architecturementioning

confidence: 99%

“…The paper proceeds as follows: section II describes the architecture of the transceiver, the upgrade from the past realization [5], [11], [12] and the tests demonstrating operation over the automotive PVT range; section III describes the implementation of the fully-adaptive algorithm; transistor-level simulations are shown in section IV for realistic automotive channels, with considerations on the transceiver's equalization strategy; conclusions are drawn in section V.…”

Section: Introductionmentioning

confidence: 99%

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Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications

Menin

Bandiziol

Grollitsch

et al. 2020

IEEE Trans. Circuits Syst. II

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This paper presents a fully-adaptive high-speed serial interface designed in 28 nm planar CMOS technology for future MIPI-compliant automotive microcontrollers operating at 12 Gb/s over long-reach channels. The transmitter has a voltage-mode driver and operates at full rate featuring an 8-tap feed-forward equalizer with tap programmability of 1/16. Transmitter's output impedance tuning is performed through activation of different driver replicas. The half-rate receiver features an analog front-end which comprises a variable-gain amplifier and a continuous-time linear equalizer. The subsequent decision-feedback equalizer has 3 programmable taps, the first of which is loop-unrolled to relax timing constraints. Another amplifier is embedded in the DFE's summing node. We employ transistor-level simulations to assess the capability of the interface to optimally adapt to realistic channels: The DFE taps and the data sampling phase are automatically adapted by means of a behavioural implementation of an LMS algorithm based on information gathered through error sampling. Such an interface was simulated on channels representing likely MIPI A-PHY to-be-defined specifications featuring up to 33 dB loss at 6 GHz.

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Means to Accelerate Transfer of Information Between Integrated Circuits

Melikyan

2023

Machine Learning-Based Design and Optimization of High-Speed Circuits

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Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm

Cited by 7 publications

References 18 publications

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications

Means to Accelerate Transfer of Information Between Integrated Circuits

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