The paper describes a 8.125-15.625 Gbps medium-reach SerDes macro for use in a networking memory system. The SerDes employs a sub-sampling ringoscillator phase-locked loop to obtain a large frequency range with low jitter performance. In addition, the transmitter uses a modified hybrid output driver and a multi-step duty-cycle corrector. The receiver uses a BERbased calibration loop to find the set of parameters that maximizes the receiver voltage margin. The transmitter output achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps with 140fs duty-cycle distortion.
A 2.3 to 5GHz LC PLL is implemented in 65nm standard CMOS for 0.6 to 10Gb/s SerDes applications. The LC VCO is measured to have 67% coarse tuning range and worstcase hold range of 9.6%. The rms random jitter (RJ rms ) on the TX output with a clock pattern is measured to be 460fs at 5GHz and 548fs at 3.125GHz. The total power dissipated from the 1.8V, 1.0V supplies is 29mW at 5GHz.
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