A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

Abstract

The paper describes a 8.125-15.625 Gbps medium-reach SerDes macro for use in a networking memory system. The SerDes employs a sub-sampling ringoscillator phase-locked loop to obtain a large frequency range with low jitter performance. In addition, the transmitter uses a modified hybrid output driver and a multi-step duty-cycle corrector. The receiver uses a BERbased calibration loop to find the set of parameters that maximizes the receiver voltage margin. The transmitter output achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps with 140fs duty-cycle distortion.

Sub-sampling PLL techniques

“…The waveform to be sampled is not necessary a sine-wave and the sub-sampling technique can also be applied to e.g. ring oscillators [7][8]. In a more advanced process, steeper voltage slopes will be available and the simple switch-cap SSPD will be able to sample faster, thus benefiting from the technology scaling.…”

“…The PD and CP noise is shown to be not multiplied by N 2 , and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the sub-sampling PLL techniques and their applications in recent PLL architectures [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Section II discusses the classical charge pump PLL.…”