A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

Vamvakos, Socrates D.; Gauthier, Claude R.; Rao, Chethan; Wang, Alvin; Canagasaby, Karthisha Ramoshan; Abugharbieh, Khaldoon; Choudhary, Prashant; Dabral, S.; Desai, Shaishav; Hassan, Mahmudul; Hsieh, Kuo-Chiang; Kleveland, B.; Mandal, Gautam; Rouse, Richard; Saraf, Ritesh; Yeung, Jason; Cao, Ying

doi:10.1007/s10470-013-0172-1

Cited by 2 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For signal integrity, a mixed signal structure CDR circuit is described. Compared with the previously works [3][4][5], this paper offers a power-efficient compatibility solution for medium data rate and low cost serial transceivers…”

Section: Introductionmentioning

confidence: 99%

“…To enable work with multiple standards, several multi-standard transceivers have been reported [3][4][5]. A 1.5-3.125 Gb/s serial transceiver was demonstrated in [3], which supported PCIe, SATA, and XAUI in 90nm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

“…Also, the LC-tank used in [4] would require more area in a digital process. A 2.488-11.2 Gbps serializer/deserializer (SerDes) transceiver in a 40 nm CMOS process is presented in [5], consuming 337 mW at 11.2 Gbps. However, it consumes relatively high power at medium data rates There are many standards and applications in this data rate range, as shown in Table 1.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

Hou

Yang

Liu

et al. 2014

Sci. China Inf. Sci.

View full text Add to dashboard Cite

A power-efficient and low-cost 1.0625-3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel (FC), Peripheral Component Interconnect Express (PCIe), and RapidIO applications. To support multiple standards with a single low power and low cost design, the transceiver presented here uses a wide swing range source-series-terminated (SST) transmitter (TX), a passive receiver (RX) equalizer, a dual-loop phase locked loop (PLL) and a mixed signal clock and data recovery (CDR) unit. The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver. The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR's reference. A CDR with a phase interpolator (PI) is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm. The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm 2. With supply voltages of 1.2 V and 3.3 V, the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at 3.125 Gb/s.

show abstract

Section: Introductionmentioning

confidence: 99%