A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

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Calibration of Mismatches in Time-Interleaved ADCs Using Teacher Learner-Based Optimization Algorithm

Chakravarthi

Chandramohan²

2022

J CIRCUIT SYST COMP

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Sampling a signal at elevated sampling rates can be easily achieved by using time-interleaved analog-to-digital converters (TIADCs). TIADCs have more than one ADC in parallel. Each ADC samples the signal with a time gap of one sampling period and hence known as TIADC. The samples from all these ADCs are combined to reconstruct the signal. But the disadvantage of TIADCs is that they have mismatches like sampling time, gain and phase offset. The proposed work focuses on estimation and correction of these mismatches. For estimation of mismatches, teacher learner-based optimization (TLBO) algorithm was used and the estimated mismatches were used for correction by applying suitable operations. The proposed algorithm was applied for four-channel TIADCs. For estimation, a pilot signal is used which in this case is a monotonic sinusoidal signal. The estimation of mismatches was accurate and the correction was implemented for TIADCs with a sinusoidal input signal and the enhancement in signal quality was evaluated by finding signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). There is a significant enhancement in SNR and SNDR. The average enhancements in SNR and SNDR are 50 and 46[Formula: see text]dB, respectively.

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A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

Cited by 3 publications

References 12 publications

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

Calibration of Mismatches in Time-Interleaved ADCs Using Teacher Learner-Based Optimization Algorithm

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