A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes

Abstract

A 2.3 to 5GHz LC PLL is implemented in 65nm standard CMOS for 0.6 to 10Gb/s SerDes applications. The LC VCO is measured to have 67% coarse tuning range and worstcase hold range of 9.6%. The rms random jitter (RJ rms ) on the TX output with a clock pattern is measured to be 460fs at 5GHz and 548fs at 3.125GHz. The total power dissipated from the 1.8V, 1.0V supplies is 29mW at 5GHz.