An 8.5–12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes

He, Yajun; Wang, Ziqiang; Liu, Han; Lv, Fangxu; Yuan, Shuai; Zhang, Chun; Wang, Zhihua; Jiang, Hanjun

doi:10.1109/mwscas.2017.8053042

Cited by 2 publications

(1 citation statement)

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“…The Ring VCO proposed in previous work [25] covers a frequency range of 8-11 GHz. It uses two differential delay cells with cross-coupled MOSFET pair in the VCO.…”

Section: Clockingmentioning

confidence: 99%

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

Chen

Wang

et al. 2021

IEEE Access

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This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a twostage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10 −12 , and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.INDEX TERMS Transceiver, feedforward equalizer, continuous-time linear equalizer (CTLE), adaptive decision-feedback equalizer (DFE), clock and data recovery (CDR).

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“…The Ring VCO proposed in previous work [25] covers a frequency range of 8-11 GHz. It uses two differential delay cells with cross-coupled MOSFET pair in the VCO.…”

Section: Clockingmentioning

confidence: 99%