An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

Chen, Hong; Wang, Dengjie; Wang, Ziqiang; Yuan, Shuai; Zhang, Chun; Wang, Zhihua

doi:10.1109/access.2021.3078844

Cited by 4 publications

(3 citation statements)

References 25 publications

(29 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Big data computing, high-definition image transmission, high-speed communication, and other related application scenarios are becoming increasingly widespread. As a result, the demand for high-speed data transmission in modern information processing is proliferating [1,2,3,4]. To compensate for the attenuation caused by the wired channel as the frequency increases [5,6,7,8,9]， equalization is introduced here to balance the non-uniformity between high and lowfrequency components and to obtain a flat amplitude frequency response and better eye diagram [10,11,12].…”

Section: Introductionmentioning

confidence: 99%

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

Chen

Cai

Zhong

et al. 2023

IEICE Electron. Express

View full text Add to dashboard Cite

In this work, a high-speed four-channel 0.8-6Gb/s wireline receiver was reported. Based on spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically adjusted to the most suitable state, avoiding the underbalanced or over-balance caused by amplitude mismatch. Moreover, a first-order semi-digital dual-loop clock and data recovery circuit (SDDCDR) with a high-speed digital loop filter (DLF) is also integrated to simplify the structure and improve the tracking ability of frequency offset. The prototype was fabricated on a 130nm CMOS process with a core area of 0.38 mm 2 for a single lane, consuming 97.3mW power at a 1.2V supply and tracking a 6966ppm frequency offset. In a 3m-cable test environment, the receiver sinusoidal jitter tolerance at high frequency is better than 0.22UI when 6Gb/s.

show abstract

Section: Introductionmentioning

confidence: 99%

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

Chen

Cai

Zhong

et al. 2023

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…DFE mainly eliminates most post-cursors based on the decision at the previous time, but it cannot eliminate precursor [5,6]. Therefore, the combined equalization of CTLE and DFE is widely adopted at the receiver [7,8,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Sun

Zhang

Yang

2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a wide rate range receiver including adaptive continuous time linear equalizer (CTLE) and loop-unrolled half rate decision feedback equalizer (DFE). A hybrid filter is adopted to expand the rate range of adaptive CTLE with spectrum balancing technology. The current-integrating summer is introduced to reduce the power of half-rate loop-unrolled DFE. The post-simulation is carried out by 0.18 μm CMOS TSMC technology and the results show that the rate range of adaptive CTLE can reach to 6.25-10 Gb/s. When the 10 Gb/s PRBS7 signal is transmitted through the 18-inch FR4 backplane with 15.451 dB loss at Nyquist frequency, the eye diagram is obviously open and its horizontal opening is about 0.9 UI.

show abstract

“…The IEEE 802.11 protocol has undergone an upgrade in the a/b/g/n/ac/ax version; its data throughput is getting higher and higher [2,3]. Transceivers are widely used in computer and mobile electronic products; protocols used vary with different applications [4].…”

Section: Introductionmentioning

confidence: 99%

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

Wang

2022

Electronics

View full text Add to dashboard Cite

The design of the analog baseband circuit is based on 55 nm CMOS technology and is integrated in an IEEE 802.11ax concurrent dual band four antenna transceiver. A low-pass filter (LPF) of the receiver was multiplexed with an LPF-transmitter such that the last three stages of the fifth order LPF-receiver were used by the LPF-transmitter, and the first programmable gain amplifier (PGA) of the receiver was partially multiplexed with the PGA-transmitter such that the PGA-receiver and the PGA-transmitter shared the same operational amplifier and input resistance, thereby reducing the power consumption, noise, linearity, and area of intermediate frequency (IF) of the transmitter designed separately. The typical bandwidth of the IF-receiver is 10/20/40 MHz; that of the IF-transmitter is 12/24/50 MHz. The gain range of the IF-receiver and the IF-transmitter is 0.1–65.5 dB and −10.1 to 3.98 dB, respectively. Under the voltage of 1.5 V, the current of the IF-receiver is 3.86 mA. As for the IF-transmitter, the current is 1.78 mA when supply voltage is 1.5 V. The input referred noise (IRN) of the IF-receiver at 10 MHz bandwidth (BW) and 62 dB gain is 14.52 nV/√ Hz, while the IRN of the IF-transmitter at 10 MHz BW and -6 dB gain is 95.16 nV/√ Hz. The suppression ability of the DC offset cancellation circuit is 35.08/80.9/110.1/113 dB. The area of the analog baseband circuit is 0.17 mm2.

show abstract

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

Cited by 4 publications

References 25 publications

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

Contact Info

Product

Resources

About