A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

Abstract

In this work, a high-speed four-channel 0.8-6Gb/s wireline receiver was reported. Based on spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically adjusted to the most suitable state, avoiding the underbalanced or over-balance caused by amplitude mismatch. Moreover, a first-order semi-digital dual-loop clock and data recovery circuit (SDDCDR) with a high-speed digital loop filter (DLF) is also integrated to simplify the structure and improve the tracking ability of frequency offset. The prototype was fabricated on a 130nm CMOS process with a core area of 0.38 mm 2 for a single lane, consuming 97.3mW power at a 1.2V supply and tracking a 6966ppm frequency offset. In a 3m-cable test environment, the receiver sinusoidal jitter tolerance at high frequency is better than 0.22UI when 6Gb/s.

Perspective Chapter: Chip I/O Design Fundamentals, Methodologies and Challenges

“…Also, as the operating frequency of ASIC application continue to increase, signal integrity on data transmission between chip I/ Os has become a bottleneck due to several types of noise, including Inter-Symbol Interference (ISI) noise, switching noise, and reflection noise [8,[12][13][14]. ISI is caused by frequency dependent attenuation of transmission channel that increases with operating frequencies and degrades noise margins, giving small eye opening and resulting in very low possibility of correct data detection and recovery [15][16][17][18]. Moreover, output drivers in advanced technologies can switch faster due to lower threshold voltage, V T , but this results a considerable supply current change in a short time (di/ dt) and causes switching noise on power supply and output voltage of drivers [19][20][21].…”