Thin crystalline silicon solar cells have the potential to achieve high efficiency due to the potential for increased voltage. Thin silicon wafers are fragile; therefore, means of support must be provided. This paper reports the design, development, and analysis of an 18-μm crystalline silicon solar cell electrically integrated with a steel alloy substrate. This ultrathin silicon is epitaxially grown on porous silicon and then transferred onto the steel substrate. This method allows the independent processing of each surface. The steel substrate enables robust handling and provides a conductive back plane. Three groups of cells with planar and textured structures are compared; significant improvements in J sc , V o c , and fill factor (FF) are achieved. The best cell shows an efficiency of 16.8% with an open-circuit voltage of 632 mV and a short-circuit current density of 34.5 mA/cm 2 .
The charge-storage
kinetics of amorphous TiO
x
nanotube electrodes
formed by anodizing three-dimensional porous Ti scaffolds are reported.
The resultant electrodes demonstrated not only superior storage capacities
and rate capability to anatase TiO
x
nanotube
electrodes but also improved areal capacities (324 μAh cm–2 at 50 μA cm–2 and 182 μAh
cm–2 at 5 mA cm–2) and cycling
stability (over 2000 cycles) over previously reported TiO
x
nanotube electrodes using planar current collectors.
Amorphous TiO
x
exhibits very different
electrochemical storage behavior from its anatase counterpart as the
majority of its storage capacity can be attributed to capacitive-like
processes with more than 74 and 95% relative contributions being attained
at 0.05 and 1 mV s–1, respectively. The kinetic
analysis revealed that the insertion/extraction process of Li+ in amorphous TiO
x
is significantly
faster than in anatase structure and controlled by both solid-state
diffusion and interfacial charge-transfer kinetics. It is concluded
that the large capacitive contribution in amorphous TiO
x
originates from its highly defective and loosely
packed structure and lack of long-range ordering, which facilitate
not only a significantly faster Li+ diffusion process (diffusion
coefficients of 2 × 10–14 to 3 × 10–13 cm2 s–1) but also more
facile interfacial charge-transfer kinetics than anatase TiO
x
.
Although Si anodes have the potential to achieve gravimetric capacities >3000 mA g −1 for Li ion batteries, their utility has been limited by their large volumetric expansion on lithiation and electrode fragmentation. We show that n-type doping reduces the lithiation potential of (100) Si and conclude that the Li ion insertion energy into crystalline Si increases with ntype dopant density. This allows tuning of the n-type dopant density in Si electrodes to reduce surface fragmentation and increase electrode cycle life. Using a combination of n-type doping, prelithiation at a low current density of 0.05 mA cm −2 and an areal capacity capping at 2 mAh cm −2 , we show that stable cycling can be achieved at a current density of 1 mA cm −2 within the potential range of 0.01−1.5 V for at least 140 cycles using an organic electrolyte without additives. Further improvements in cyclability can be achieved by using alternative electrolytes with greater electrochemical stability at low potentials. Because of the massively reduced cost of Si wafers, heavily doped wafer-based current collectors may present an alternative to Si thin film anodes with improved adhesion between the current collector and electroactive Si surface provided that the wafers can be sufficiently thin to reduce electrode mass and volume. Alternatively, n-type doping of Si can be used to reduce fragmentation in particle-based electrodes permitting more controllable lithiation and a longer cycle life.
Copper‐plated interconnects were widely adopted for volume manufacture of integrated circuits after more than a decade of intensive research to demonstrate that use of Cu would not impact device reliability. However, although Cu‐plated metallisation promises significantly reduced costs for Si photovoltaics, its adoption in manufacturing has not gained the same traction. This review identifies some key challenges facing the introduction of Cu‐plated metallisation for Si photovoltaics. These include the following: (1) increased carrier recombination due to the use of Cu for metal contact formation; (2) reduced module reliability due to adhesion or contact integrity failures; and (3) limited availability of cost‐effective processes and equipment for metal plating. For integrated circuits, Cu's low electrical resistance and high resistance to electromigration provided an impetus for the large investment in process development that was required to realise Cu‐plated interconnects. However, the technical advantages of using Cu for Si solar cell contacts are not as compelling, as solar cells can tolerate larger feature sizes thus reducing the criticality of the contact metal's conductivity and electromigration properties. Additionally, for Si photovoltaics, low cost is paramount, and new challenges arise from the need for modules to absorb light and operate in the field for 25+ years in diverse outdoor climates. However, with the scale of Si photovoltaic manufacturing expected to increase dramatically in the next decade, the use of large quantities of silver for cell metallisation will provide an incentive to address reliability concerns regarding the use of Cu for Si photovoltaic metallisation.
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