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A. AHMAD²The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.

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This paper presents a realistic test approach suitable to Design For Testability (DFT) and BuiltIn Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safereliable -testable digital logic designs.

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