Design of a Realistic Test Simulator For a Built-In Self Test Environment

Abstract

This paper presents a realistic test approach suitable to Design For Testability (DFT) and BuiltIn Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safereliable -testable digital logic designs.

On determination of LFSR structures to assure more reliable and secure designs of cryptographic systems

“…statistical tests is to investigate strings which is the key stream eudo random generator. There fforts carried out on numerous applied to a PN sequence to gth [33], [37] - [39]. Some of est (X 2 -Test) st, on property tion property AL AND APPROACH t a required strong key we re in the form of flow chart as ting the Berlekamp Massey of the PN sequence properties ython language.…”

“…The processes of ciphering and deciphering are known as encryption and decryption respectively. Encrypted messages can sometimes be broken by cryptanalysis, also called code breaking [12] - [23], [26] - [35], [37] - [41]. There are two main types of management principles in cryptography namely secret key and public key.…”

A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)

“…All possible initial loading of PRTPG, 2 n -1, are exhausted to monitor the aliasing error behaviour of MISR-SAZ. These characteristic polynomials are generated using the algorithms developed and reported in papers [2], [40] and [41]. To make it more readable the simulation procedure used to study the aliasing behaviour is described below.…”

“…This task is accomplished by testing the circuit. System maintenance draws heavily upon the testing capability of the logic system [1], [2]. Digital circuit manufacturers are well aware of the need to incorporate testability features early in the design stage, or otherwise they have to incur higher testing costs, subsequently.…”

What Causes to Tune a Condition of Exactly Identical Fault-Masks Behaviors in an LFSR based BIST Methodology

“…In recent years, numerous Built-In Self-Test (BIST) systems have been proposed just because of its gaining acceptance in the VLSI industry due to its popular enormous advantages [1][2][3][4][5][6] .With BIST methodology, there is no need to use external test equipment sincea self-testable circuitry is built on the chip itself. The BIST technique usually combines a built-in Pseudo-Random Test-Sequence (PRTS) generation with an output response analyzer.…”