On Properties of PN Sequences Generated by LFSR – a Generalized Study and Simulation Modeling

Ahmad, Afaq

doi:10.17485/ijst/2013/v6i10.16

Cited by 7 publications

(4 citation statements)

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“…Some studies have been made on the simulation of LFSR using Matlab and Simulink [8]. However, the method presented in this work use Scilab and offers many opportunities.…”

Section: Discussionmentioning

confidence: 99%

Modeling and Simulation of CDMA Codes in Scilab

Diagana¹,

Gueye²

2015

IJCNS

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Prior to hardware implementation, simulation is an important step in the study of systems such as Direct Sequence Code Division Multiple Access (DS-CDMA). A useful technique is presented, allowing to model and simulate Linear Feedback Shift Register (LFSR) for CDMA. It uses the Scilab package and its modeling tool for dynamical systems Xcos. PN-Generators are designed for the quadrature-phase modulation and the Gold Code Generator for Global Positioning System (GPS). This study gives a great flexibility in the conception of LFSR and the analysis of Maximum Length Sequences (MLS) used by spread spectrum systems. Interesting results have been obtained, which allow the verification of generated sequences and their exploitation by signal processing tools.

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“…Some studies have been made on the simulation of LFSR using Matlab and Simulink [8]. However, the method presented in this work use Scilab and offers many opportunities.…”

Section: Discussionmentioning

confidence: 99%

Modeling and Simulation of CDMA Codes in Scilab

Diagana¹,

Gueye²

2015

IJCNS

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“…With the aid of a linear feedback shift register, the PN Succession generator demonstrated here creates a sequence of pseudorandom binary digits. The output sequence has a period of length 2 m − 1, here, m = 128 44 . The feedback polynomial utilized in this example is X 128 + X 126 + X 101 + X 99 + 1.…”

Section: Proposed Methodology and Experimental Setupmentioning

confidence: 99%

“…The output sequence has a period of length 2 m − 1, here, m = 128. 44 The feedback polynomial utilized in this example is X 128 + X 126 + X 101 + X 99 + 1.…”

Section: Proposed Methodology and Experimental Setupmentioning

confidence: 99%

Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT

Chhabra

Lata

2022

Security and Privacy

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The global market of developing Internet of Things (IoT) devices increases rapidly with improved design goals like cost, energy efficiency, and performance. Unfortunately, the above design goals often come at the expense of security. Illegal access to the network, malicious device control, compromised sensitive information, and theft of personal data are main threats to these devices. As a result, the Advanced Encryption Standard (AES) is sometimes employed to ensure safe transmission and processing of data in IoT Systems.However, tampering, cloning, and reverse engineering are main concerns that impair the computational complexity of the 128-bit AES at the hardware level. Recently hardware obfuscation-based AES has emerged as a comprehensive hardware security approach for reducing threat impacts. The hardware obfuscation schemes efficiently introduce obfuscation keys for AES to conceal its functionality. The Xilinx Vivado 2016.2 software and BASYS-3 FPGA have been used to implement obfuscated AES approaches in this work. The proposed methods have low resource usage in terms of area and power overhead while providing a high level of security in terms of Hamming Distance of 50% and Avalanche Effect of 40% for each obfuscation method. We have also analyzed the probability of success for brute-force attacks for proposed methodologies.

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“…(1) 0 -Digital pseudo-noise generator (DPNG) to synthesize additive white Gaussian noise signal [10].…”

Section: Digital Convolution Algorithm In Time Domain For Dmfmentioning

confidence: 99%

Untitled

2024

INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN COMPUTER AND COMM

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In this paper, we discuss a practical mechanism of digital matched filtering which maximizes of output SNR for square, triangular , Gaussian pulse signals and other pulse signals in presence of additive white Gaussian noise (AWGN) by using a digital matched filter (DMF) corresponding to time domain convolution algorithm of input and reference signals using Cyclone II EP2C70F896C6 FPGA from ALTERA placed on education and development board DE2-70 with the following parameters: sampling frequency MHz F sam 50  , pulse width 1  INP SNR , processing gain factor is 25dB. The results of filter operation are evaluated using a digital oscilloscope to display the input and output signals for different INP SNR .

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On Properties of PN Sequences Generated by LFSR – a Generalized Study and Simulation Modeling

Cited by 7 publications

References 0 publications

Modeling and Simulation of CDMA Codes in Scilab

Modeling and Simulation of CDMA Codes in Scilab

Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT

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