Achievement of higher testability goals through the modification of shift registers in LFSR-based testing

Abstract

A. AHMAD²The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.

A New Type of NLFSR Functions with Maximum Periods

“…FSR is one of the most efficient ways to generate pseudorandom sequences. FSR has several applications such as authentication [1], cryptography [2], testing [3], and data compression [4]. FSR has mainly two types: Linear Feedback Shift Register (LFSR) and Non-Linear Feedback Shift Register (NLFSR).…”

On Sequence Lengths of Some Special External Exclusive OR Type LFSR Structures – Study and Analysis

“…Some of the application areas are Built-In Self-Test (BIST) for Very Large Scale Integration (VLSI) circuits' design, cryptography applications like stream ciphers, and error correction and detection codes. In addition, PRBS have been commonly used in the fields of digital signal processing, wireless communications, direct sequence spread spectrum, scrambling &descrambling, encryption & decryption, steganography, and many more (Williams 1984;McCluskey 1985, Bardell et al 1987Nanda et al 1989, Ahmad 1997Jamil and Ahmad 2002;Ahmad 2005aAhmad , 2012Ahmad , 2013aHell and Johansson 2008, Mukherjee et al 2011.…”

A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)

“…An empirical relationship, that have been used for estimating the cost of finding a faulty chip, indicates that the cost increases by a factor of 10, as fault finding advances from one level to the next [3] - [7]. However, recent studies have shown that the cost of testing and fault finding, at system and field level, is higher than this factor of 10 and increases exponentially [7] - [9]. Thus, if a fault can be detected at chip or board level, then significantly larger costs per fault can be avoided.…”