Weak Inversion for Ultimate Low- Power Logic

Vittoz, E.A.

doi:10.1201/9781420039559.ch16

Cited by 17 publications

(21 citation statements)

References 0 publications

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“…This observation does not contradict with similar results for conventional CMOS, where (16) as shown in [6]. However, the influence of on is quite different in conventional CMOS, where an optimum value to minimize can be found, especially for small values, due to the significant leakage in CMOS.…”

Section: Performance Analysis and Observationssupporting

confidence: 75%

“…T HE demand for implementing ultra-low-power digital systems in many modern applications such as mobile systems [1], [2], sensor networks [3], [4], and implanted biomedical systems [5], has increased the importance of designing logic circuits in subthreshold regime [6]. In subthreshold MOSFET operation, current density is very low and the ratio of the transconductance to bias current of the device is maximum [7], [8].…”

Section: Introductionmentioning

confidence: 99%

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Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Tajalli

Brauer

Leblebici

et al. 2008

IEEE J. Solid-State Circuits

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106

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Abstract-This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

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Section: Performance Analysis and Observationssupporting

confidence: 75%

Section: Introductionmentioning

confidence: 99%

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Tajalli

Brauer

Leblebici

et al. 2008

IEEE J. Solid-State Circuits

Self Cite

106

View full text Add to dashboard Cite

show abstract

“…Special circuit techniques have been implemented to enable operation at very low current levels and to achieve the desired performance specifications. The demand for implementing ultra-low-power digital systems in many modern applications such as mobile systems [4], sensor networks [5,6], and implanted biomedical systems [7], has increased the importance of designing logic circuits in sub-threshold regime [8].…”

Section: Introductionmentioning

confidence: 99%

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Rai¹,

Mishra²,

Tiwari³

2013

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This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 µm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

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“…T HE demand for ultra-low power and low voltage integrated circuits is making the design of CMOS integrated circuits in the subthreshold/weak inversion region [1] increasingly attractive. Applications such as sensor networks, wearable battery-powered systems, and implantable circuits for biological applications require the implementation of circuits with very low power consumption as well as low sensitivity to the supply voltage and its variations [2]- [5].…”

Section: Introductionmentioning

confidence: 99%

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

Tajalli

Alioto

Leblebici

2009

IEEE Trans. Circuits Syst. II

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Abstract-This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-μm CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.Index Terms-Source-coupled logic (SCL), subthreshold SCL (STSCL), ultralow-power circuits, weak inversion SCL (WiSCL).

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Weak Inversion for Ultimate Low- Power Logic

Cited by 17 publications

References 0 publications

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

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