Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

Tajalli, Armin; Alioto, Massimo; Leblebici, Yusuf

doi:10.1109/tcsii.2008.2011603

Cited by 24 publications

(13 citation statements)

References 11 publications

(12 reference statements)

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“…1, the MOS transistor in subthreshold region can be modeled either as a current source for high values of (100 mV or more), or as a linear resistance given by (6) for low values of (less than 25-30 mV). Apparently, these models do not apply for intermediate values of…”

Section: A Simplified Large-signal Transistor Models In Subthresholdmentioning

confidence: 99%

“…Until now, the design of robust subthreshold circuits has been pursued by following either the voltage-mode [3]- [5] or current-mode approach [6]- [11]. The voltage-mode approach, Manuscript which includes the static CMOS logic style, is able to achieve a low power while using roughly the same design flow as super-threshold logic.…”

Section: Introductionmentioning

confidence: 99%

“…The voltage-mode approach, Manuscript which includes the static CMOS logic style, is able to achieve a low power while using roughly the same design flow as super-threshold logic. On the other hand, the current-mode approach is able to further reduce the power consumption, but the development of the design flow requires a higher effort [6]- [11].…”

Section: Introductionmentioning

confidence: 99%

“…In the case of current-mode logic, these aspects are currently well understood [6]- [11]. On the other hand, in the case of static CMOS logic, only the first two have been extensively investigated, whereas the DC behavior and the noise immunity are not well understood, as previous analyses rely on intuitive arguments or very simplistic assumptions that are not verified in practical cases.…”

Section: Introductionmentioning

confidence: 99%

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Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Alioto

2010

IEEE Trans. Circuits Syst. I

154

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In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.Index Terms-DC behavior, noise immunity, subthreshold CMOS logic, ultra-low power, VLSI.

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Section: A Simplified Large-signal Transistor Models In Subthresholdmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Alioto

2010

IEEE Trans. Circuits Syst. I

154

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“…However, due to body biasing of devices, circuits should be implemented in triple well technologies. A novel circuit implementation in subthreshold region using source coupled logic (SCL) in order to increased reliability is presented by Tajali [14]. A novel method for increasing subthreshold frequency of operation by using parallel transistor stacks is presented by Muker and Shams [15].…”

Section: Year Application Referencementioning

confidence: 99%

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

Shiran¹

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This thesis addresses the challenge of designing reliable and energy-efficient subthreshold flip-flops. A dual-clock-phase flip-flop (TG-FF) and a single-clock-phase flip-flop (SP-FF) configurations are considered and their gradual design modifications are reported towards perfecting their yields at minimum cost in terms of energy consumption. In addition, the two optimized flip-flop designs are compared based on the criteria of static and dynamic energy consumptions, delay, and reliability in face of PVT variations.A 65 nm and a newer 28 nm CMOS technology kit were used during the course of this work. Multi-threshold MOSFETs and transistor sizing technique were incorporated for yield optimization. In general we were able to increase the flip-flops reliabilities to 100% at the nominal temperature and power supply condition, and in the worst-case around 90% in the extreme cold and -10% noise on the power supply. We also prove the overall superiority of the SP-FF compared to TG-FF. i Acknowledgment First and foremost, I would like to express my deep and sincere gratitude to my supervisor Professor Maitham Shams for the continuous support, understanding, kindness, and great guidance. During my studies, he not only helped me in my research but also he taught me in my life.

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Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

Chanda

Chakraborty

Sarkar

2015

Int J Numerical Modelling

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Summary In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.

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Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

Cited by 24 publications

References 11 publications

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

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