Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

Chanda, Manash; Chakraborty, Ananda Sankar; Sarkar, Chandan Kumar

doi:10.1002/jnm.2053

Cited by 8 publications

(3 citation statements)

References 22 publications

(45 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the proposed device can be preferred over Junction-less Double Gate MOSFET for high-speed [37][38][39][40] and lowpower consumption applications in the subthreshold regime as a possible candidate to replace conventional CMOS devices 11 (c). From 11 (d), it is obvious that in the sub-threshold regime, significant logic swing [41][42] can be obtained which also proves the efficacy of the device in the sub-threshold regime [43][44][45][46][47][48].…”

Section: Cmos Inverter Based On the Proposed Devicementioning

confidence: 73%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

View full text Add to dashboard Cite

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

show abstract

Section: Cmos Inverter Based On the Proposed Devicementioning

confidence: 73%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

View full text Add to dashboard Cite

show abstract

“…Therefore, there is no optimum value at the PDP curve of the HTFET-based resistive inverter. Finally, our proposed work is compared with some state-ofthe-art technologies (Chanda et al, 2018;Chanda et al, 2015). The power dissipation of a single stage adiabatic inverter is computed and compared with conventional CMOS inverter (Chanda et al, 2018), for which a performance matrix, called "energy gain" is defined.…”

Section: Circuit Implementation and Resultsmentioning

confidence: 99%

“…The delay modeling of the CMOS inverter is computed in Chanda et al (2015) at the sub-threshold region of operation for low power applications. The comparative study reveals that the propagation delay of our HTFET-based inverter is some fraction of nano-seconds (0.81 ns approximately), whereas it is few tens of nano-seconds (10–20 ns approximately) for CMOS inverter operated in sub-threshold region with same design considerations.…”

Section: Circuit Implementation and Resultsmentioning

confidence: 99%

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Ghosh

Venkateswaran

Sarkar

2021

View full text Add to dashboard Cite

Purpose High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit. Design/methodology/approach Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances. Findings The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter. Originality/value Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

show abstract

Analysis of the subthreshold CMOS logic inverter

Sharroush

2018

Ain Shams Engineering Journal

View full text Add to dashboard Cite

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

Cited by 8 publications

References 22 publications

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Analysis of the subthreshold CMOS logic inverter

Contact Info

Product

Resources

About