In this paper, we describe the interface specification and core block design methods for Run Length Coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We design VLSI architecture of run length coder using VHDL. This design can achieve the high performance for video coder, is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the Variable Length Coding. Run Length Coder is implemented by register transfer level(RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5um CMOS, 3.3K technology and reuse as core IP(Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and total 1,536 bits of Static RAM.Fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse to multimedia system and digital video applications.