A bs t r ac t This paper describes a new FPGA architecture which relies on a proprietary antifuse technology coupled with 0.8 micron CMOS technology. In this architecture, individual CMOS transistors, not just logic blocks, can be configured to match MPGA macrocells transistor for transistor. Small mux like blocks are also available for logic or latch functions or collectively as configurable static RAMS. The architecture supports macrocell libraries with delay and resource usages similar to commercial 1.5 micron MPGA libraries.
This paper describes how Crosspoint programs antifuses in its fine grain architecture. It compares the programming circuits used by Crosspoint to the circuits used by Actel and Quicklogic. Every antifuse in Crosspoint's FPGA can be uniquely programmed using a three dimensional addressing scheme to independently drive each electrode of the antifuse. The circuitry supports 10 volt programming and 13.5ma programming current to any target antifuse. Although the programming overhead is high, the antifuses are programmed to an average 50 Cl resistance, thus providing for high performance operation of the FPGA.
Advances in IC process technology have enabled the design of complex systems on a single chip. System-on-chip developers need to be able to mix and match pre-designed, best-in-class functional blocks from many providers if they are to meet design deadlines with limited design engineering resources. Consequently, there is a rising interest in the creation, distribution, and design application of reusable, interoperable blocks of intellectual property, referred to as "IP" or "virtual components." This panel will explore the opportunities and challenges for design innovation offered by a worldwide, open reuse mechanism for virtual components.
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