An MPGA Compatible FPGA Architecture

Marple, David; Cooke, Larry

doi:10.1109/cicc.1992.591107

Cited by 21 publications

(10 citation statements)

References 7 publications

(5 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Although we expect these blocks to be used infrequently, the roles they serve in asynchronous circuits are essential, and are not implementable in standard digital logic. Thus, they must appear as special, built-in blocks in any FPGA which hopes to implement asynchronous circuits, but which does not allow mappings to program circuits at the transistor level (for an example of an EPGA which might allow sufficient transistor-level programming to implement an arbiter, see [Marple 1992]). For examples of how both types of blocks are used, please see figure 4.…”

Section: Fumentioning

confidence: 99%

MONTAGE: An FPGA for synchronous and asynchronous circuits

Hauck

Borriello

Burns

et al. 1993

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Field-programmable gate arrays are frequently used to implement system interfaces and glue logic. However, there has been little attention given to the special problems of these types of circuits in FPGA architectures. In this paper we describe Montage, a Triptych-based FPGA designed for implementing asynchronous logic and interfacing separately-clocked synchronous circuits. Asynchronous circuits have different requirements than synchronous circuits, which make standard FPGAs unusable for asynchronous applications. At the same time, many asynchronous design methodologies allow components with greatly different performance to be substituted for one another, making a design environment which migrates between FPGA, MPGA, and semi-custom implementations very attractive. Similar problems also exist for interfacing separately-clocked synchronous circuits. We discuss these problems, and demonstrate how the Montage FPGA satisfies the demands of these classes of circuits.

show abstract

Section: Fumentioning

confidence: 99%

MONTAGE: An FPGA for synchronous and asynchronous circuits

Hauck

Borriello

Burns

et al. 1993

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…As used in the original gate arrays, the most simple and un-specific way of providing this capability is to use a transistor as the basic logic element, and build gates and storage elements from it. This approach was indeed attempted in a commercial FPGA from the now-defunct company Crosspoint [144]. This kind of very fine-grained logic block, however, requires the use of large amounts of programmable interconnect to create any typical logic function.…”

Section: Fpga Logic Block Fundamentals and Trade-offsmentioning

confidence: 99%

“…FPGA architects over the last two decades have selected basic logic blocks made of transistors (noted above) [144], NAND gates [160], an interconnection of multiplexers [79], lookup tables [49], and PAL-style wide-input gates [217]. These choices were originally driven by intuitive insights on the part of architects, typically with very little data or analysis, with a few exceptions [79].…”

Section: Fpga Logic Block Fundamentals and Trade-offsmentioning

confidence: 99%

“…By this definition, a dedicated flip-flop inside a logic block is considered a hard circuit structure, since it is possible to build flip-flops from an interconnection of programmable LUTs or gates. Dedicated flip-flops are now universally used in commercial FPGAs, although some early FPGAs were built without them [1,144]. In addition, modern commercial FPGAs contain dedicated logic within each general purpose block to support arithmetic carry and sum functions [18,21,22,23,24,25,221,224,225,227,228,229,231] and some memory functions [23,231].…”

Section: Heterogeneitymentioning

confidence: 99%

See 1 more Smart Citation

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

View full text Add to dashboard Cite

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

show abstract

“…Base logic units are most typically implemented as LUTs [9], but NAND gates [10], transistors [11], and multiplexers [12] have also been used. A homogeneous FPGA is an FPGA that consists of only base logic units and programmable routing.…”

Section: Definitions For Modern Fpgasmentioning

confidence: 99%

A verilog RTL synthesis tool for heterogeneous FPGAs

Jamieson¹,

Rose²

International Conference on Field Programmable Logic and Applications, 2005.

View full text Add to dashboard Cite

Modern heterogeneous FPGAs contain "hard" specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible "soft" programmable logic and routing. These hard structures provide major benefits, yet raise interesting questions in FPGA CAD and architecture. To develop high-quality CAD mapping algorithms for these structures, and indeed to measure the quality of proposed new structures in the architectural domain, it is essential to have a flexible tool at the RTL synthesis level that permits heterogeneous FPGA CAD and architecture experimentation. In this paper we present a synthesis tool, called Odin, and an algorithm that permits flexible targeting of hard structures in FPGAs. Odin maps Verilog designs to two different FPGA CAD flows: Altera's Quartus, and the academic VPR CAD flow. We have expended significant effort to make the quality of this tool comparable to an industrial front-end synthesis tool, and we present mapping results for our benchmarks that show the quality of our results.

show abstract

An MPGA Compatible FPGA Architecture

Cited by 21 publications

References 7 publications

MONTAGE: An FPGA for synchronous and asynchronous circuits

MONTAGE: An FPGA for synchronous and asynchronous circuits

FPGA Architecture: Survey and Challenges

A verilog RTL synthesis tool for heterogeneous FPGAs

Contact Info

Product

Resources

About