A verilog RTL synthesis tool for heterogeneous FPGAs

Abstract

Modern heterogeneous FPGAs contain "hard" specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible "soft" programmable logic and routing. These hard structures provide major benefits, yet raise interesting questions in FPGA CAD and architecture. To develop high-quality CAD mapping algorithms for these structures, and indeed to measure the quality of proposed new structures in the architectural domain, it is essential to have a flexible tool at the RTL synthesis level that permits heterogeneous FPGA CAD and architecture experimentation. In this paper we present a synthesis tool, called Odin, and an algorithm that permits flexible targeting of hard structures in FPGAs. Odin maps Verilog designs to two different FPGA CAD flows: Altera's Quartus, and the academic VPR CAD flow. We have expended significant effort to make the quality of this tool comparable to an industrial front-end synthesis tool, and we present mapping results for our benchmarks that show the quality of our results.

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

“…The BLIF output file, in the FPGA CAD flow, is then read by ABC and the CAD flow continues to map the design to an FPGA as described in the previous section. [1]. In the future, we will be adding these extensions to Odin II, noting that the software structure has been designed to easily add these features.…”

“…Once the AST is created, an elaborator then traverses the AST to create a flattened netlist of the design (for more details on this process please see the original paper on Odin [1]). The netlist data-structure within Odin II that stores this netlist has been carefully designed to allow it to be easily manipulated.…”

“…However, Odin II is inherently a general synthesis framework that can be used to target any CAD flow. Odin II affords significant advantages over the original Odin [1] synthesis tool as Odin II provides a unified customizable front-end HDL synthesis environment.…”

“…Odin II's output can be fed into traditional back-end flows for both FPGAs and ASICs so that these improvements can be better quantified. Whereas the original Odin [1] provided an open source synthesis tool, Odin II's synthesis framework offers significant improvements such as a unified environment for both front-end parsing and netlist flattening. Odin II also interfaces directly with VPR [2], a common academic FPGA CAD flow, allowing an architectural description of a target FPGA as an input to enable identification and mapping of design features to custom features.…”

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

“…We could get the .blif file from verilog RTL file by ODIN II [16] and ABC [17]. The T-VPACK [13] program packs LUTs and flip-flops into CLB which contains one or more Logic Elements (LEs) in .net format for each module.…”