In this paper, we describe the interface specification and core block design methods for Run Length Coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We design VLSI architecture of run length coder using VHDL. This design can achieve the high performance for video coder, is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the Variable Length Coding. Run Length Coder is implemented by register transfer level(RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5um CMOS, 3.3K technology and reuse as core IP(Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and total 1,536 bits of Static RAM.Fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse to multimedia system and digital video applications.
In this paper, we present a simple parallel architecture for Discrete Wavelet Transform (DWT). Efficient computation of the pyramid algorithm for the computing of the discrete wavelet transform is possible due to the similarity between computation results of each octave. By using similarity, we separated filter into 2 parts, even filter and odd filter. 1 octave and other octave computation are pcrformed in even and odd filter at the same time. Proposed architecture has following features. 1) Critical path is 1 multiply and 1 adder, 2) Number of required register is l+J*( rLd21-1) + 1+J*( [L1/21 -1) + J , where J is the number of octaves ,I-h is length of highpass filter and LI is length of lowpass filter.
In this paper, we describe the design and implementationof code division multiple access (CDhU) base station demodulator (CBD) ASIC for the use in IS9.5-based CDMA mobile communication system. We propose a novel design method for the noncoherent OQPSK YN cowelator, fast Hadamard transfomier (FHv, lock detector, and time tracking loop, which are the main fitwctional blocks of the demodulator. We also present the implementation environment for the design and verification of demodulator ASIC. The chip has been designed using cell-based design methodology and fabricated by double-metal 0.8-pn CMOS technology. The die of the chip measures 8. I x 8.3 mm and it contain approximately 76,000 logic gates and 3,000 bits of static RAM.
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