VLSI implementation of a 200-MHz 16×16 left-to-right carry-free multiplier in 0.35 μm CMOS technology for next-generation DSPs

Kolagotla, R.K.; Srinivas, H.R.; Burns, G.

doi:10.1109/cicc.1997.606669

Cited by 20 publications

(17 citation statements)

References 7 publications

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“…We find that the right-to-left array multiplier without a fast final adder needs 59 unit delays, while the left-to-right array multiplier with on-the-fly converters takes only 42 unit delays. Therefore, the 8 × 8 left-to-right full-width multiplier is about 28% faster than the right-to-left full-width multiplier, and this estimation is close to that reported in [5]. There still exist rooms for speed improvement for the basic left-to-right multiplier.…”

Section: Conventional Left-to-right Full-width Multipliersupporting

confidence: 63%

“…The block diagram of a left-to-right full-width multiplier is shown in Fig. 3 described in [5]. The circuit between the dashed lines is used to interface the added converters to the original array.…”

Section: Conventional Left-to-right Full-width Multipliermentioning

confidence: 99%

“…Recently, the left-to-right algorithm without a final carry propagation step [4]- [5] had been proposed in an attempt to improve the performance of the right-to-left algorithm. More recently, the work [6] [7] used several kinds of compressors in the LSB parts of the partial product reduction array to further increase the operating speed of a left-to-right multiplier.…”

Section: Introductionmentioning

confidence: 99%

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Low-power fixed-width array multipliers

Wang

Kuo

Yang

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%.

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Section: Conventional Left-to-right Full-width Multipliersupporting

confidence: 63%

Section: Conventional Left-to-right Full-width Multipliermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-power fixed-width array multipliers

Wang

Kuo

Yang

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…In the first group the optimization is done by manipulating the sub-blocks of the multiplier such as full adders and logic gates [3]. In the second category a new structure is proposed for multipliers based on the bus width and other parameters [4]. In this paper an efficient algorithm is used to minimize the delay of the whole multiplier block by minimizing the delay of intermediate stages via transistor sizing.…”

Section: Introductionmentioning

confidence: 99%

Speed improvement algorithm for 16×16 multipliers using sizing optimization

Eghbalkhah

Afzal

Afzali-Kusha

2007

2007 International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

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In this paper the speed improvement of a 16×16 multiplier is addressed via sizing of the transistors used in multiplying blocks. Genetic algorithm (GA) is used to calculate the appropriate W for transistors. Modification of W/L ratio of transistors has reduced the multiplier delay up to 16 percent under different supply voltages and technologies with respect to the case of transistors having non-optimized but common W/L ratios. The algorithm is implemented in Matlab and circuit simulations are done using HSpice for 0.18 um, 0.13 um, 100 nm and 70 nm Static CMOS technologies. The multiplier is simulated with different supply voltages in each technology.

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“…The optimal final adder for tree multipliers is CSMA based design [16]. Efficient design of on-the-fly converter for L-R array multipliers also corresponds to a multi-level carryselect (CSEL) or conditional-sum (CSUM) adders [11]. In [19], generalized earliest-first (GEF) algorithm was proposed to design CSUM for arbitrary input arrival profile.…”

Section: Final Addermentioning

confidence: 99%

High-performance left-to-right array multiplier design

Huang¹,

Ercegovac²

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed design shows equivalent performance as tree multipliers for n ≤ 32. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. The partial products are split into upper and lower groups. Each group is reduced using [3:2] adders with optimized signal flows and the carry-save results from two groups are combined using a [4:2] adder. The final product is obtained with a prefix adder optimized to match the non-uniform arrival profile of the inputs. Layout experiments indicate that upper/lower split multipliers have slightly less area and power than optimized tree multipliers while keeping the same delay for n ≤ 32.

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VLSI implementation of a 200-MHz 16×16 left-to-right carry-free multiplier in 0.35 μm CMOS technology for next-generation DSPs

Cited by 20 publications

References 7 publications

Low-power fixed-width array multipliers

Low-power fixed-width array multipliers

Speed improvement algorithm for 16×16 multipliers using sizing optimization

High-performance left-to-right array multiplier design

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VLSI implementation of a 200-MHz 16×16 left-to-right carry-free multiplier in 0.35 μm CMOS technology for next-generation DSPs

Cited by 20 publications

References 7 publications

Low-power fixed-width array multipliers

Low-power fixed-width array multipliers

Speed improvement algorithm for 16&#x00D7;16 multipliers using sizing optimization

High-performance left-to-right array multiplier design

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Product

Resources

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Speed improvement algorithm for 16×16 multipliers using sizing optimization