Speed improvement algorithm for 16×16 multipliers using sizing optimization

Abstract

In this paper the speed improvement of a 16×16 multiplier is addressed via sizing of the transistors used in multiplying blocks. Genetic algorithm (GA) is used to calculate the appropriate W for transistors. Modification of W/L ratio of transistors has reduced the multiplier delay up to 16 percent under different supply voltages and technologies with respect to the case of transistors having non-optimized but common W/L ratios. The algorithm is implemented in Matlab and circuit simulations are done using HSpice for 0.18 um, 0.13 um, 100 nm and 70 nm Static CMOS technologies. The multiplier is simulated with different supply voltages in each technology.