Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder

Riaz, Muhammad; Ahmed, Syed Adrees; Javaid, Qasim; Kamal, Tariq

doi:10.1109/ibcast.2018.8312254

Cited by 10 publications

(2 citation statements)

References 8 publications

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“…In 17 , the authors modified the carry-select adder (CSA) using a binary to excess-1 (BEC1) converter and used this circuit as a compressor to implement the circuit of the Dadda multiplier, which improved the speed, area, and energy as compared to the traditional CSA-based design. To reduce power and area, an optimized adder with pass transistor logic is used to design a dadda multiplier in 18 , but the output voltage levels are not as strong as in CMOS logic. The authors proposed a Dadda circuit based on the carry look-ahead adder and optimized full adder in 19 , which was implemented using complex cells in CMOS 65 nm technology.…”

Section: Introductionmentioning

confidence: 99%

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Munawar

Shabbir

Akram

2023

J CIRCUIT SYST COMP

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The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50[Formula: see text]nm, 90[Formula: see text]nm, and 120[Formula: see text]nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33[Formula: see text]GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50[Formula: see text]nm technology consumes 25[Formula: see text]uW of power at 3.33[Formula: see text]GHz with 76[Formula: see text]ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

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Section: Introductionmentioning

confidence: 99%

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Munawar

Shabbir

Akram

2023

J CIRCUIT SYST COMP

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“…Dadda algorithm can be used for 16-bit or higher order multiplication but with the increase in number of bits, the complexity also increases. For a 4-bit Dadda multiplier, the maximum tree height of partial products is four and reduction stages are three [16]. When the same algorithm is utilized to perform 8-bit multiplication, the tree height increases to six and reduction stages increase to four [17], thereby increasing the resources consumption and delay.…”

Section: Introductionmentioning

confidence: 99%

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

et al. 2019

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A unique design for an optimized N-bit multiplier is proposed and implemented which utilizes a modified divide-andconquer technique. The conventional technique requires four N/2-bit multipliers to perform N-bit multiplication, whereas the proposed design uses only one multiplier module in hardware to perform the functionality of four modules. It uses Dadda algorithm in its multiplier module. It has been implemented using Verilog HDL, and a good accuracy of results was observed in simulations which effectively verify its functionality. Design was also synthesized on various FPGAs including Spartan 3E, Virtex-5 and Virtex-7. Performance summary, after place and route, showed that the proposed approach significantly reduces hardware utilization. Furthermore, the proposed design is almost 75% more efficient in terms of resources utilization and operating frequency as compared to the conventional design.

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FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

Palanisamy

Ramachandran²

2020

Circuit Theory & Apps

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SummaryFor ultra‐low‐power applications, the computing components are smaller in size and consume less energy. In nonstationary signal analysis, the transformation plays an important role. Out of different transformation techniques, the most famous and dominant architecture is the discrete wavelet transform. The building block of the architecture should be optimized by all parameters. In this paper, the optimization was done on the power reduction and leakage current reduction. A new FinFET‐based lifting‐based wavelet architecture was proposed. Power gating and reversible logic methodology are proposed for the FinFET‐based transform to reduce the dynamic power by about 30%. The proposed FinFET‐based processing elements were utilized in the various blocks of the lifting‐based DWT architecture. The implementation was done in 32‐nm CMOS and FinFET technology. From the results, it has been investigated that the FinFET‐based circuits are efficient when compared with CMOS technology. This is due to the second‐order effects happening in CMOS circuits below 45 nm. The proposed design consumes less area and low leakage current and power when compared with the CMOS technology. Future trends of using multigate devices below 14 nm technology are presented finally.

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Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder

Cited by 10 publications

References 8 publications

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Area, Delay, and Energy-Efficient Full Dadda Multiplier

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

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