Area, Delay, and Energy-Efficient Full Dadda Multiplier

Abstract

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50[Formula: see text]nm, 90[Formula: see text]nm, and 120[Formula: see text]nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33[Formula: see text]GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50[Formula: see text]nm technology consumes 25[Formula: see text]uW of power at 3.33[Formula: see text]GHz with 76[Formula: see text]ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.