FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

Abstract

SummaryFor ultra‐low‐power applications, the computing components are smaller in size and consume less energy. In nonstationary signal analysis, the transformation plays an important role. Out of different transformation techniques, the most famous and dominant architecture is the discrete wavelet transform. The building block of the architecture should be optimized by all parameters. In this paper, the optimization was done on the power reduction and leakage current reduction. A new FinFET‐based lifting‐based wavelet architecture was proposed. Power gating and reversible logic methodology are proposed for the FinFET‐based transform to reduce the dynamic power by about 30%. The proposed FinFET‐based processing elements were utilized in the various blocks of the lifting‐based DWT architecture. The implementation was done in 32‐nm CMOS and FinFET technology. From the results, it has been investigated that the FinFET‐based circuits are efficient when compared with CMOS technology. This is due to the second‐order effects happening in CMOS circuits below 45 nm. The proposed design consumes less area and low leakage current and power when compared with the CMOS technology. Future trends of using multigate devices below 14 nm technology are presented finally.

A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

“…10 GCs in the ULP class (e.g., 4T 10 ) have a prolonged speed (kHz to MHz), and the cells with higher speeds (such as TG 3T 9 ) are in the LP consumer class or even more power-hungry one. 4 Accordingly, our proposed cell is simultaneously in the ULP and high-speed VLSI SoC classes. The proposed 5T cell can be used as a cache memory in ULP and high-speed applications due to 1-GHz clock frequency, ultra-low (pW range) leakage and retention power consumption, and the compact area compared to other GC-eDRAM cells.…”

“…Figure 1 shows the structure of DG FinFET. FinFETs better block short‐channel effects compared to planar MOSFETs, allowing transistor scaling thanks to better control over the channel 4 . The other advantages are higher drain current, faster switching speed, lower leakage current, and low power (LP) consumption.…”

“…FinFETs better block short-channel effects compared to planar MOSFETs, allowing transistor scaling thanks to better control over the channel. 4 The other advantages are higher drain current, faster switching speed, lower leakage current, and low power (LP) consumption. Considering these benefits, ultra-low power (ULP)embedded memories are designed in very large-scale integration (VLSI) SoCs suitable for biomedical or remote sensing applications while meeting area and speed concerns.…”

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

“…Therefore, researchers have resorted to reversible logic to overcome the high power of CMOS circuits. Common characteristics of the reversible‐based circuits are forbidden fan‐out (FO), forbidden loops and feedbacks, minimum useless outputs (known as Garbage), minimum possible delay time, the minimum number of constant inputs (known as Ancilla inputs like constant “0” and “1”), minimum quantum costs (such as minimum use of basic gates), and the equal number of inputs and outputs to create an n × n reversible circuit 16,17 . Various reversible gates such as Feynman gate, Fredkin gate, Toffoli gate, Peres gate, R‐gate, and TR gate have been proposed in the literature.…”

“…Common characteristics of the reversible-based circuits are forbidden fan-out (FO), forbidden loops and feedbacks, minimum useless outputs (known as Garbage), minimum possible delay time, the minimum number of constant inputs (known as Ancilla inputs like constant "0" and "1"), minimum quantum costs (such as minimum use of basic gates), and the equal number of inputs and outputs to create an n  n reversible circuit. 16,17 Various reversible gates such as Feynman gate, Fredkin gate, Toffoli gate, Peres gate, R-gate, and TR gate have been proposed in the literature. The most substantial factors that can jeopardize the performance of reversible circuits are the misuse of reversible gates, which can be referred to as a large number of garbage outputs and ancilla inputs, or even incorrect use of the used technique leads to voltage swing drop.…”