An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

Abstract

A unique design for an optimized N-bit multiplier is proposed and implemented which utilizes a modified divide-andconquer technique. The conventional technique requires four N/2-bit multipliers to perform N-bit multiplication, whereas the proposed design uses only one multiplier module in hardware to perform the functionality of four modules. It uses Dadda algorithm in its multiplier module. It has been implemented using Verilog HDL, and a good accuracy of results was observed in simulations which effectively verify its functionality. Design was also synthesized on various FPGAs including Spartan 3E, Virtex-5 and Virtex-7. Performance summary, after place and route, showed that the proposed approach significantly reduces hardware utilization. Furthermore, the proposed design is almost 75% more efficient in terms of resources utilization and operating frequency as compared to the conventional design.

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

“…As a result, the power consumption and performance constraints of the multiplier are essential 4 . The add-and-shift operation of the array multiplier produces more partial products (PP) than the tree multiplier, boosting Power and Delay 5 . Despite having fewer components than an array multiplier, the PPs are organized in rows or columns and have extensive interconnections 6 .…”

“…Researchers have also employed Nikhilam and UT multiplication methods. Due to the simultaneous creation and addition of the PPs, the former approach is quick 5 . Beneficial takeaways from both sutras have been made, and a novel architecture for quick and effective multiplication has been constructed 26 .…”