A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi, C. M.; Sabeenian, R. S.

doi:10.1038/s41598-023-49913-5

Cited by 2 publications

(2 citation statements)

References 46 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Area Slice LUT utilization Akshay Savji et. al (1) 54.037 6% Swati Shetkar et.al (2) 43.65 4% Nuriddin Safoev et.al (3) 4.25 5% Mansi Jhamb et.al (4) 13.921 3% C. M. Kalaiselvi et.al (5) 15.83 4% VijendraBairwa et.al (6) 11…”

Section: Existing Methods Parameters Delay In Nsmentioning

confidence: 99%

“…Although the performance of the hybrid logic types is promising, the majority of these adders have poor driving capabilities, and if the appropriately designed buffers are not included, their performance significantly deteriorates in the cascaded mode of operation. To enhance the performance of the Vedic multiplier, the encoding technique of Radix-2 and Radix-4 encoding is the best method (5) . The primary drawback of the Radix method is that it requires complex multiplication and complex addition.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

View full text Add to dashboard Cite

Objectives: This work objective is to construct an FPGA-based 16x16 Vedic multiplier and assess the performance of the multiplier using three distinct architectures: pipeline, wave pipeline, and modified wave pipeline in terms of delay and clock skew. Methods: The 16 × 16 Vedic multiplier was constructed and designed through four numbers of an 8x8 Vedic multiplier. For the 16x16 Vedic multiplier, the 3-stage pipeline and wave pipeline techniques are applied, and the delay performances of the Vedic multiplier are compared. Delay optimization: In the wave pipeline Vedic multiplier architecture, the delay is decreased by inserting the known delay on the longest path delay between the multiplier and adder. Clock skew optimization: The clock skew issue of the wave pipeline Vedic multiplier architecture is minimized by adjusting the setup time violation of the clock signal that is connected to the input and output registers. Findings: The delay performance of the Vedic multiplier was evaluated by the synthesis tools Xilinx 12.1, Xilinx ISE 14.2, and Altera, and based on the synthesis report, the Xilinx synthesis tool offers 73.71% delay performance for the pipeline approach and 53.39% for the wave pipeline approach compared to the Altera tool. Further delay is reduced by the proposed modified wave pipeline approach, which saves 2.122 ns of delay compared to the wave pipeline architecture. The clock skew performance was analyzed using the Time Quest timing analyzer tool, and it was minimized to 0.035 from 0.048 compared to the wave pipeline approach. Novelty: In this work, the modified wave pipeline approach has been applied to the existing Vedic multiplier architecture, and it offers less delay as well as less clock skew compared to the existing method. Hence, the performance of the Vedic multiplier with a modified wave pipelined approach was evaluated through a 3-tap FIR filter by applying a vibroarthrography signal. Keywords: Pipeline, Wave Pipeline, Vedic Multiplier, Clock skew, Set up violation, Altera quartex- II Time quest timing analyzer tool

show abstract

Section: Existing Methods Parameters Delay In Nsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

View full text Add to dashboard Cite

show abstract

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Kalaiselvi,

Sabeenian

2024

Analog Integr Circ Sig Process

Self Cite

View full text Add to dashboard Cite

Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the FPGA implementation employing VLSI design approaches and parallel computing technology. Signal processing, machine learning, and recon gurable computing research should be closely monitored as arti cial intelligence develops. To enable deep learning algorithms, continued research should be done on energy-constrained computing technology. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in ALU, Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a speci c hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.

show abstract

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Cited by 2 publications

References 46 publications

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Contact Info

Product

Resources

About