Low-power fixed-width array multipliers

Wang, Jinn‐Shyan; Kuo, Chien-Nan; Yang, Tsung‐Han

doi:10.1145/1013235.1013311

Cited by 20 publications

(8 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This segment gives a brief explanation about some of the traditional parallel unsigned multipliers. Wang et al [13] proposed a multiplier circuit based on the Add and Shift algorithm. Although this proposed array multiplier is easy to design, it is very slow because of its long critical path and it requires less area.…”

Section: Related Workmentioning

confidence: 99%

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Deepa¹,

Marimuthu²

2019

Sādhanā

View full text Add to dashboard Cite

In current day situation we come across numerous mathematical challenges. This could be overwhelmed by the Vedic Mathematics. Vedic Mathematics is an ancient approach to solve problems in a rapid manner. In this paper the design of a novel Vedic square and multiplier architecture based on Yavadunam Sutra is proposed. Yavadunam is a squaring sutra of the Vedic Mathematics. We have designed a generic architecture for this squaring sutra and have designed a high speed Vedic binary multiplier architecture using the principles of Yavadunam sutra. The proposed multiplier offers significant improvement in speed. Xilinx Spartan FPGA is used to design and realize the architecture and the Synopsys device with 90 nm and 180 nm technology is used to synthesize the same.

show abstract

Section: Related Workmentioning

confidence: 99%

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Deepa¹,

Marimuthu²

2019

Sādhanā

View full text Add to dashboard Cite

show abstract

“…To reduce this error, we have two correction techniques in the literature, namely constant correction and variable correction techniques were implemented in [10][11][12][13][14][15], [21]. Even though the constant correction bias technique [10][11] is simpler than variable correction bias technique [12][13][14][15], the truncation error is more since the bias cannot be adjusted adaptively by the input vectors. Since the accuracy of fixed-width multiplier is a trade-off with area cost, we have the different fixed-width multipliers in the literature [21].…”

Section: Fundamentals Of Fixed-width Parallel Array Multipliermentioning

confidence: 99%

“…Intense research has been done to develop efficient multipliers with fixed-width output [10][11][12][13][14][15][16], [20] which provide output at a required degree of precision without excessive hardware requirements. Analysis shows that the zero average probability of input signals is over 73.8% [18] in the conventional DSP and multimedia applications.…”

Section: Introductionmentioning

confidence: 99%

Fixed - Width Multiplier Circuits Using Column Bypassing and Decompositon Logic Techniques

Balamurugan¹,

Mallick²

2015

ijeei

View full text Add to dashboard Cite

This paper presents, low power signed and unsigned fixed-width multipliers using the column bypassing technique with carry save adder array structure. We have decomposed the partial products into two parts and executed them in parallel to reduce the delay of proposed fixed-width array multiplier. The proposed multiplier reduces the power consumption by skipping the unwanted switching activity when the multiplicand operand consists of a number of zeros. This work evaluates the power, delay and area of fixed-width multipliers and shows that the proposed array multiplier consumes less power and has reduced delay compared to the conventional fixed-width array multipliers.

show abstract

“…From this figure, we can also find that the proposed multiplier has better power efficiency than the existing multipliers. Designs [2], [5], and [7] are 32-bit multipliers which are considered as reference indexes only.…”

Section: Comparisonmentioning

confidence: 99%

“…The design [7] involves a fixed-width 32-bit left-to-right multiplier which obtains 8% speed improvement, 14% power reduction, and 13% area saving. Meanwhile, design [8] explores a design methodology for high-speed modified Booth multipliers.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique

Chen

Chu

Chen

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e. using registers and using AND gates, to assert the data signals of multipliers after the data transition. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. By adopting a 0.18-µm CMOS technology, the proposed SPST-equipped multiplier dissipates only 0.0121 mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction.

show abstract

Low-power fixed-width array multipliers

Cited by 20 publications

References 9 publications

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Fixed - Width Multiplier Circuits Using Column Bypassing and Decompositon Logic Techniques

A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique

Contact Info

Product

Resources

About