Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Deepa, A.; Marimuthu, C. N.

doi:10.1007/s12046-019-1180-3

Cited by 15 publications

(6 citation statements)

References 11 publications

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“…The current multipliers and squarers (precisely their related adders), which form the central part of these systems, affect their speed and area [18]. The more complex squarers and multipliers or their related adders are, the more they influence the rate and size [2,24].…”

Section: Methodsmentioning

confidence: 99%

“…The squaring operation represents one of the most arithmetic operations in high-speed applications involved cryptography, animation, image compression, fast-Fourier transform (FTT), pattern recognition, adaptive filtering, and others [1][2][3]. Although squaring function is executed by utilizing multipliers such as Booth, Wallace tree, Dadda, or Vedic multiplier, commonly, performing squaring function by multiplication needs recurring addition operations that incur consuming the computing-time and unnecessarily increasing the area of overall design [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

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Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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“…Moreover, by squaring it the result is obtained. This sutra achieves less delay and area by implementing Synopsys devices with 90nm and 180nm technology [14].…”

Section: Related Workmentioning

confidence: 99%

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Kalaiselvi,

Sabeenian

2024

Analog Integr Circ Sig Process

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Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the FPGA implementation employing VLSI design approaches and parallel computing technology. Signal processing, machine learning, and recon gurable computing research should be closely monitored as arti cial intelligence develops. To enable deep learning algorithms, continued research should be done on energy-constrained computing technology. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in ALU, Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a speci c hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.

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“…Table 2 illustrates the strategies and procedures that Tirthaji created to reinforce the rules found in 16 sutras and 13 up-sutras, which were called Vedic Mathematics. The Nikhilam and Urdhva sutras were the focus of most investigations for the development of multipliers 25 . Researchers have also employed Nikhilam and UT multiplication methods.…”

Section: Related Workmentioning

confidence: 99%

“…One drawback of the current technique is that it takes up more space and has a bigger delay in the PPR (second stage of the multiplication phase) 25 , 33 , 34 . All previously substantiated Vedic systems can handle only unsigned integers, which summarises the complexity of the proposed technique.…”

Section: Related Workmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

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Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Cited by 15 publications

References 11 publications

Vedic-Based Squarers with High Performance

Vedic-Based Squarers with High Performance

Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

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