High-performance left-to-right array multiplier design

Huang, Zhijun; Ercegovac, M.D.

doi:10.1109/arith.2003.1207654

Cited by 23 publications

(18 citation statements)

References 20 publications

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“…In the TP implementation made in MB, [2] adopts modified booth encoder and decoder are shown in Figure 2(a) & (b). Different methodologies of implementing MB recoding logic are explained in [13,14].…”

Section: Tp Implementation In Modified Boothmentioning

confidence: 99%

An optimised twin precision multiplier for ASIC environment

Asirvatham¹,

Ramachandran²

2015

EURASIP J. Adv. Signal Process.

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In this paper, we present the performance of twin precision technique in reduced computation modified booth (RCMB) multiplier to achieve double throughput, and an algorithm is proposed. Twin precision technique is the efficient way to obtain double throughput in the multipliers. We describe how to apply twin precision technique to RCMB multipliers. Implementation of twin precision in RCMB multiplier requires lesser changes to be made in partial product array for obtaining double throughput. Multiplexers usually do the signal selection for N and N/2 bit multiplication. In RCMB multiplier, [N/2] + 1 partial product are reduced to N/2 rows. Our idea of implementing twin precision technique to RCMB results in less utilisation of multiplexers of about [N/2] + 3 which gave a way for optimization in the twin precision (TP) multiplier. Thereby, we have achieved the drastic reduction in multiplexer utilisation of about 40% to 50% (for N = 8 to 128) compared to the existing twin precision modified booth multiplier. In our proposed optimised TP modified booth multiplier this reduction in multiplexers gave a way for overall reduction in area, power and delay. Lesser utilisation of multiplexer results in the area reduction of about 5% to 18%, delay of 5% to 20% and a considerable reduction in power of 8% to 32% were noticed in the proposed TP booth multiplier for N = 8 to 128. Our proposed optimised TP multiplier is implemented in FFT complex multiplication which is taken as an application case study and achieves better performance (area, delay and power) compare to prior TP multiplier. All our evaluation are made using cadence RTL compiler using TSMC 180 nm library.

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Section: Tp Implementation In Modified Boothmentioning

confidence: 99%

An optimised twin precision multiplier for ASIC environment

Asirvatham¹,

Ramachandran²

2015

EURASIP J. Adv. Signal Process.

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“…Huang and Ercegovac [8] presented the arithmetic details about the signal gating schemes and showed 10% to 45% power reduction for adders. The combination of the Signal Flow Optimization (SFO), left-to-right leapfrog structure, and upper/lower split structure was incorporated in the design to optimize the array multipliers by Huang and Ercegovac [9] and it is reported that the new approach can save about 20% power dissipation. Wen et al [10] reported that for the known output, some columns in the multiplier can be turned off and it reduces 10% power consumption for random inputs.…”

Section: Mmadheswaran Professor Department Of Ece Muthayammal Enginmentioning

confidence: 99%

Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications

Madheswaran¹,

Saravanan²

2010

IJCA

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This paper explores the design approach of a low power high performance Multiply and Accumulate (MAC) unit with Hybrid Encoded Reduced Transition Activity Technique (HERTAT) equipped multiplier and low power 0.13µm adder. The developed low power MAC unit is verified for image processing systems exploiting insignificant bits in pixels values and the similarity of neighboring pixels in video streams. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. If the number of 1's less than or equal to three the proposed encoding technique used otherwise go for Booth technique. The proposed adder cell used in the MAC block consumes less power than the other previous adder techniques. This high performance low power MAC can be used in image processing. It is observed from the device level simulation using TANNER 12.6 EDA, that the proposed scheme helps to reduce the switching activities in the MAC unit up to 19% and saves power up to 46%.

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“…Finally, other techniques to optimize multiplication focus on fine-grained manipulations that are suitable for ASIC or custom implementations [22][23][24] [25]. However, because FPGAs are multipurpose devices, they must support more general multiplication structures.…”

Section: Related Workmentioning

confidence: 99%

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

Srinath

Compton

2010

Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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The introduction of asymmetric embedded multiplier blocks in recent Xilinx FPGAs complicates the design of larger multiplier sizes. The two different input bitwidths of the embedded multipliers lead to two different shifting factors for the partial products that must be summed. This makes even the most straightforward multiplier design less intuitive. In this thesis, I present a methodology and set of equations to automatically generate Verilog hardware description code for arbitrary multiplier sizes composed of arbitrarily-sized asymmetric embedded multiplier cores. The presented technique also uses intelligent rearrangement of the multiplier block outputs into partial product terms to reduce the overall delay of the circuit. Multipliers created with this generator are faster and use fewer DSP blocks than either those created using Xilinx Core Generator or those created by simply using the '*' operator in Verilog. It also uses fewer LUTs than those created using the '*' operator. Finally, the presented generator can create multipliers larger than possible with Core Generator, and is limited only by the number of available embedded multipliers.4 Acknowledgement I would like to thank my advisor Katherine Compton for providing me the opportunity to pursue this research under her supervision. I thank her for the invaluable guidance and support she has extended throughout the duration of my degree.

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High-performance left-to-right array multiplier design

Cited by 23 publications

References 20 publications

An optimised twin precision multiplier for ASIC environment

An optimised twin precision multiplier for ASIC environment

Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

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