Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

Abstract

The introduction of asymmetric embedded multiplier blocks in recent Xilinx FPGAs complicates the design of larger multiplier sizes. The two different input bitwidths of the embedded multipliers lead to two different shifting factors for the partial products that must be summed. This makes even the most straightforward multiplier design less intuitive. In this thesis, I present a methodology and set of equations to automatically generate Verilog hardware description code for arbitrary multiplier sizes composed of arbitrarily-sized asymmetric embedded multiplier cores. The presented technique also uses intelligent rearrangement of the multiplier block outputs into partial product terms to reduce the overall delay of the circuit. Multipliers created with this generator are faster and use fewer DSP blocks than either those created using Xilinx Core Generator or those created by simply using the '*' operator in Verilog. It also uses fewer LUTs than those created using the '*' operator. Finally, the presented generator can create multipliers larger than possible with Core Generator, and is limited only by the number of available embedded multipliers.4 Acknowledgement I would like to thank my advisor Katherine Compton for providing me the opportunity to pursue this research under her supervision. I thank her for the invaluable guidance and support she has extended throughout the duration of my degree.

Asymmetric large size multipliers with optimised FPGA resource utilisation

“…All results are presented in terms of the following metrics: delay, number of LUTs used number of embedded multipliers required and power consumptions. The proposed architectures are compared also with two other approaches: one generated by commercial tools, which we refer to as vendor synthesis tool (VST) method, and one based on the OI method [9]. A Xilinx Virtex-5 FPGA was targeted, and the tool, Xilinx' ISE-13.1, was used.…”

“…The embedded multipliers in FPGAs are used efficiently, and the improvements in speed and area usages have been achieved by using these approaches. An approach targeting asymmetric large size unsigned multipliers is proposed by Srinath and Compton [9]. This technique simply groups the partial products of the multiplication as a diagonal architecture and separates the partial products into three regions.…”

Sequential Large Multipliers on FPGAs

“…Authors report syntheses results for 48 by 34 to 216 by 170 multiplier implementations. The syntheses results show that the proposed methods in [21] map larger multipliers than the ones mapped by FPGA provider's synthesis tool onto the similar platforms.…”

“…In this context, there exist ASIC implementations of large multipliers [7] but recent studies focus on FPGA implementations that use built-in arithmetic blocks provided in modern FPGAs [3,5,11,12,15,21].…”

“…In [21], methods to optimize the design of combinational large multipliers via efficient use of asymmetric multiplier blocks are presented. Automatized generation of the HDL code for large multipliers is provided.…”