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Residue Number System (RNS) has been extensively used in high-speed applications. It inherits the advantages of parallelism and modularity, which lead to fault tolerance property. Since carry propagation is limited to each module in RNS, errors do not propagate inter-moduli. Indeed, due to the restriction in carry propagation and fault tolerance property, RNS can be promisingly fast and reliable that makes it a favorable encoding for the digital systems which are highly prone to noise like communication channels. By adding some extra moduli, the so-called redundant RNS (RRNS) is gained. Although several methods around RRNS have already been proposed in the literature, the structures without need for extra moduli have not been introduced yet. This paper addresses three Error Detection and Correction (EDC) schemes for RNS based on parity structures. Using these techniques, the low power fault-tolerant RNS methods with low complexity are presented. Synthesis results using 180[Formula: see text]nm CMOS standard cell library show that the proposed architectures for the three-moduli set [Formula: see text] are in average 17%, 52% and 44% more efficient than the conventional RRNS in terms of delay, power consumption, and area overhead, respectively, without losing the EDC capability.
Residue Number System (RNS) has been extensively used in high-speed applications. It inherits the advantages of parallelism and modularity, which lead to fault tolerance property. Since carry propagation is limited to each module in RNS, errors do not propagate inter-moduli. Indeed, due to the restriction in carry propagation and fault tolerance property, RNS can be promisingly fast and reliable that makes it a favorable encoding for the digital systems which are highly prone to noise like communication channels. By adding some extra moduli, the so-called redundant RNS (RRNS) is gained. Although several methods around RRNS have already been proposed in the literature, the structures without need for extra moduli have not been introduced yet. This paper addresses three Error Detection and Correction (EDC) schemes for RNS based on parity structures. Using these techniques, the low power fault-tolerant RNS methods with low complexity are presented. Synthesis results using 180[Formula: see text]nm CMOS standard cell library show that the proposed architectures for the three-moduli set [Formula: see text] are in average 17%, 52% and 44% more efficient than the conventional RRNS in terms of delay, power consumption, and area overhead, respectively, without losing the EDC capability.
Residue Number Systems (RNS) demonstrate the fascinating potential to serve integer addition/multiplication-intensive applications. The complexity of Artificial Intelligence (AI) models has grown enormously in recent years. From a computer system’s perspective, ensuring the training of these large-scale AI models within an adequate time and energy consumption has become a big concern. Matrix multiplication is a dominant subroutine in many prevailing AI models, with an addition/multiplication-intensive attribute. However, the data type of matrix multiplication within machine learning training typically requires real numbers, which indicates that RNS benefits for integer applications cannot be directly gained by AI training. The state-of-the-art RNS real number encodings, including floating-point and fixed-point, have defects and can be further enhanced. To transform default RNS benefits to the efficiency of large-scale AI training, we propose a low-cost and high-accuracy RNS fixed-point representation: Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling Down Postprocessing Multiplication (SD-Post-Mul) . Moreover, we extend the implementation details of the other two RNS fixed-point methods: Double RNS Concatenation (D-RNS-Concat) and Single RNS Logical Partition (S-RNS-Logic-P) representation with Scaling Down Preprocessing Multiplication (SD-Pre-Mul) . We also design the architectures of these three fixed-point multipliers. In empirical experiments, our S-RNS-Logic-P representation with SD-Post-Mul method achieves less latency and energy overhead while maintaining good accuracy. Furthermore, this method can easily extend to the Redundant Residue Number System (RRNS) to raise the efficiency of error-tolerant domains, such as improving the error correction efficiency of quantum computing.
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