Vertical architecture for enhancement mode power transistors based on GaN nanowires

Abstract

The demonstration of vertical GaN wrap-around gated field-effect transistors using GaN nanowires is reported. The nanowires with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source-drain voltages (Vds), the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next-generation GaN-based power devices.

GaN Nanowire Schottky Barrier Diodes

“…The enhancement mode GaN nanowire power transistors with an unintentionally doped drift region have been reported in [18] [18]. The FoM for the fabricated and the simulated NWs is plotted in Fig.…”

“…-2 ·eV -1 [18] in the non-polar a-plane which is used in this work. The current path also includes the highly doped and high TD dense region near the base of the NWs.…”

“…This approach has been investigated for InAs wrap gated nanowire transistors [17] and more recently GaN enhancement mode power transistors having breakdown voltage of 100-140 V [18]. However, the NW power transistors have an unintentionally doped drift layer and exhibit significantly lower Figure of Merits (FoM) than the vertical GaN devices reported.…”

Nanofabrication of Vertically Aligned 3D GaN Nanowire Arrays with Sub-50 nm Feature Sizes Using Nanosphere Lift-off Lithography

“…A 90° SEM image shows the remaining pyramidal chromium mask shape (Figure 3d). In contrast to commonly used Cl2-based GaN dry etching, the nanowires were fabricated in a hybrid top-down approach combining ICP-DRIE etching with SF6/H2 gases and KOH-based wet chemical etching [5,6]. The ICP-DRIE process was performed with the following initial recipe: an ICP power of 800 W, an HF power of 275 W, SF6 and H2 flow rates of 12 and 100 sccm, respectively, a pressure of 1 Pa, and at room temperature.…”

Enhancement-mode Ga2O3 wrap-gate fin field-effect transistors on native (100) β-Ga2O3 substrate with high breakdown voltage

“…A V BK exceeding 600-V at V GS ¼ 0 V off-state was demonstrated and represents the highest breakdown voltage measured without fieldplate for b-Ga 2 O 3 transistors, and the highest breakdown for any transistor technology utilizing non-planar device channels. [20][21][22][35][36][37] Future work includes understanding the role of traps at the dielectric-Ga 2 O 3 interface and optimizing onresistance by reducing the fin channel length and using highly doped ohmic cap layer. …”