Variable-length input huffman coding for system-on-a-chip test

Abstract

This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new Variable-length Input Huffman Coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, whencompared to three previous approaches [1][2][3], which reduce some test data compression environment's parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously.

A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment

“…As pointed out in [16], symbol-based schemes (e.g., [4,17]) can efficiently exploit correlations in the specified bits and do not require ATPG constraints, while linear techniques (e.g., [9,10]) is easy for implementation. In this work, we mainly target symbol-based test compression schemes.…”

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

“…It is because the large numbers of unspecified values make many long runs. Table 4 shows a comparison between the compression rates for the proposed methods and those for the existing test compressions, namely Huffman coding and the combination of Huffman and run-length coding not using the interleaving, run-length coding [5], Golomb coding [6], Frequencydirected run-length (FDR) coding [7], and variable-length input Huffman coding (VIHC) [8]. The block size for Huffman coding b is set to nine.…”

“…Therefore, the approaches are not available to IP cores if core vendors provide system integrators with only test cubes and the system integrators do not know the structural information about the IP cores. Test compression using the following coding can be categorized into the latter class: statistical coding such as Huffman coding and selective Huffman coding [4], run-length coding [5], Golomb coding [6], FDR coding [7] and VIHC [8]. Although the approaches do not provide as efficient compression as the approaches categorized into the former class, they can be applied to IP cores as long as system integrators know test Manuscript received July 8, 2008.…”

A compression-driven test access mechanism design approach

“…Previous work analysis for TDC and TAM design are detailed in [12,17] and [8], respectively. In addition to the area penalty involved with TDC, inserting TDC in a design also requires an increase in control overhead.…”

“…TDC has been approached from a number of research directions. For example, methods which (i) exploit the sparseness of care bits in the test set have been proposed in [2,6,17], and methods which (ii) exploit the regularities within the test set have been proposed in [5,12,18,21].…”